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Register definition
Field
7
Ninth Data Bit for Receiver
R8
When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the
left of the msb of the buffered data in the SCI_D register. When reading 9-bit data, read R8 before reading
SCI_D because reading SCI_D completes automatic flag clearing sequences that could allow R8 and
SCI_D to be overwritten with new data.
6
Ninth Data Bit for Transmitter
T8
When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the
left of the msb of the data in the SCI_D register. When writing 9-bit data, the entire 9-bit value is
transferred to the SCI shift register after SCI_D is written so T8 should be written, if it needs to change
from its previous value, before SCI_D is written. If T8 does not need to change in the new value, such as
when it is used to generate mark or space parity, it need not be written each time SCI_D is written.
5
TxD Pin Direction in Single-Wire Mode
TXDIR
When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines
the direction of data at the TxD pin.
0
TxD pin is an input in single-wire mode.
1
TxD pin is an output in single-wire mode.
4
Transmit Data Inversion
TXINV
Setting this bit reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
0
Transmit data not inverted.
1
Transmit data inverted.
3
Overrun Interrupt Enable
ORIE
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0
OR interrupts disabled; use polling.
1
Hardware interrupt requested when OR is set.
2
Noise Error Interrupt Enable
NEIE
This bit enables the noise flag (NF) to generate hardware interrupt requests.
0
NF interrupts disabled; use polling).
1
Hardware interrupt requested when NF is set.
1
Framing Error Interrupt Enable
FEIE
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0
FE interrupts disabled; use polling).
1
Hardware interrupt requested when FE is set.
0
Parity Error Interrupt Enable
PEIE
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0
PF interrupts disabled; use polling).
1
Hardware interrupt requested when PF is set.
408
SCIx_C3 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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