Begin- And End-Trigger - NXP Semiconductors MC9S08SU16 Reference Manual

trigger to the ICE logic to begin or end capturing information into the FIFO. In the case
of an end-type (DBG_T[BEGIN] = 0) trace run, the qualified comparator signal stops the
FIFO from capturing any more information.
If a CPU breakpoint is also enabled, you would want DBG_C[TAG] and
DBG_T[TRGSEL] to agree so that the CPU break occurs at the same place in the
application program as the FIFO stopped capturing information. If DBG_T[TRGSEL]
was 0 and DBG_C[TAG] was 1 in an end-type trace run, the FIFO would stop capturing
as soon as the comparator address matched, but the CPU would continue running until a
TAG signal could propagate through the CPUs instruction queue, which could take a long
time in the case where changes of flow caused the instruction queue to be flushed. If
DBG_T[TRGSEL] was one and DBG_C[TAG] was zero in an end-type trace run, the
CPU would break before the comparator match signal could propagate through the
opcode tracking logic to end the trace run.
In begin-type trace runs (DBG_T[BEGIN] = 1), the start of FIFO capturing is triggered
by the qualified comparator signals, and the CPU breakpoint (if enabled by
DBG_C[BRKEN]=1) is triggered when the FIFO becomes full. Since this FIFO full
condition does not correspond to the execution of a tagged instruction, it would not make
sense to use DBG_C[TAG] = 1 for a begin-type trace run.

28.4.4.1 Begin- and end-trigger

The definition of begin- and end-trigger as used in the DBG module are as follows:
• Begin-trigger: storage in FIFO occurs after the trigger and continues until 8 locations
are filled.
• End-trigger: storage in FIFO occurs until the trigger with the least recent data falling
out of the FIFO if more than 8 words are collected.
28.4.4.2 Arming the DBG module
Arming occurs by enabling the DBG module by setting the DBG_C[DBGEN] bit and by
setting the DBG_C[ARM] bit. The DBG_C[ARM] and DBG_S[ARMF] bits are cleared
when the trigger condition is met in end-trigger mode or when the FIFO is filled in begin-
trigger mode. In the case of an end-trace where DBG_C[DBGEN] = 1 and
DBG_T[BEGIN] = 0, DBG_C[ARM] and DBG_S[ARMF] are cleared by any reset to
end the trace run that was in progress. The DBG_S[ARMF] bit is also cleared if
DBG_C[ARM] is written to zero or when the DBG_C[DBGEN] bit is low. The TBC
logic determines whether a trigger condition has been met based on the trigger mode and
the trigger selection.
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 28 Debug module (DBG)
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