Register Definition; Ics Control Register 1 (Ics_C1) - NXP Semiconductors MC9S08SU16 Reference Manual

Register definition

12.3 Register definition
Absolute
address
(hex)
1848

ICS Control Register 1 (ICS_C1)

1849 ICS Control Register 2 (ICS_C2)
184A ICS Control Register 3 (ICS_C3)
184B ICS Control Register 4 (ICS_C4)
184C ICS Status Register (ICS_S)
12.3.1 ICS Control Register 1 (ICS_C1)
Address: 1848h base + 0h offset = 1848h
Bit 7
Read
CLKS
Write
Reset
0
Field
7–6 Clock Source Select
CLKS
Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value
of ICS_C2[BDIV].
00 Output of FLL is selected.
01 Internal reference clock is selected.
10 External reference clock is selected.
11 Reserved, defaults to 00.
5–3 Reference Divider
RDIV
Changing RDIV will cause the change of reference clock frequency of FLL, RDIV is not allowed to be
changed in FEE/FBE mode.
Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting
frequency must be in the range 31.25 kHz to 39.0625 kHz.
192
ICS memory map
Register name
6 5
RDIV
0 0
ICS_C1 field descriptions
RDIV SIM_SOPT1[RANGE]= 0
000
001
010
011
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
(in bits)
8 R/W
8 R/W
8 R/W
8 R/W
8
4 3
IREFS
0 0
Description
1
1
2
4
8
Section/
Reset value
page
04h 12.3.1/192
20h 12.3.2/193
See section 12.3.3/194
See section 12.3.4/195
R 10h 12.3.5/196
2 1
IRCLKEN Reserved
1 0
SIM_SOPT1[RANGE]= 1
32
64
128
256
NXP Semiconductors
0
0