Mcu Block Diagram - NXP Semiconductors MC9S08SU16 Reference Manual

MCU block diagram

2.2.9 Human-machine interfaces
The following human-machine interfaces (HMI) are available on this device:
Module
Port Control (PORT)
Keyboard Interrupts (KBI)
2.3 MCU block diagram
The block diagram below shows the structure of the MCUs.
BKGD
I2C
SCI IRQ
40
Table 2-10. HMI modules
Some general purpose input or output pins are capable of interrupt request
generation.
• Up to eight keyboard interrupt pins with individual pin enable bits
• Each keyboard interrupt pin is programmable
• One software-enabled keyboard interrupt
• Exit from low-power modes
S08L Core
Memory
CPU
Map
Controller
Background
Interrupt
Debg
Unit
Controller
Clock Generation
Interrupt Priority
Internal Clock Source(ICS)
Internal
32 kHz
FLL
Watchdog (WCOP)
Low Power Osc (LPO)
Internal
20 kHz LPO
Inter-Module
FTM PWT PDB
Crossbar
0,1
Ch0,1 Ch0,1
Inter Module Crossbar Inputs
Inter Module Crossbar Outputs
GPIO Port A&B&C and Peripheral MUX
Package Pins
Figure 2-1. Block diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
S08L Bus
Peripheral
Bus Bridge
Cyclic Redundancy
Controller
Check (CRC)
Windowed
Power Management
Controller (PMC)
Modulo Timer System Integration
(MTIM)
Peripheral Bus
Analog Signals
CMP ADC1
ADC0
+ 6-bit DAC 12-bit
12-bit
Package Pins
User Flash
16 KB (SU16)
8 KB (SU8)
User RAM
768 Bytes
Module (SIM)
Gate Pre-Driver Unit (GDU)
PWM
Predriver + 5 CMP + 2 OPAMP
Pre
Driver Analog Inpus
Motor Drive
NXP Semiconductors