Table of Contents
Advertisement
Memory map and register definition
When a digital peripheral module or system function is selected and enabled on a pin,
reads of this register still returns the pin value of the associated pin if PTCDD[0] = 0.
When a shared analog function is selected for a pin, all digital pin functions are disabled.
A read of this register returns a value of 0 for any bits that have shared analog functions
enabled.
A write of valid data to this register must occur before setting the direction control bit of
an associated port pin. This ensures that the pin will not be driven with an incorrect data
value.
Address: 0h base + 2h offset = 2h
Bit
7
Read
Write
Reset
0
Field
7–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Port C Data Register Bits
PTCD
For port C pins that are configured as inputs, a read returns the logic level on the pin.
For port C pins that are configured as outputs, a read returns the last value that was written to this
register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
8.5.4 Port A Direction Register (PORT_PTADD)
Address: 0h base + 3h offset = 3h
Bit
7
Read
Write
Reset
0
Field
PTADD
Port A Direction Register Bits
These bits control the direction of port A pins and what is read for PTAD reads.
0
Pin is configured as general-purpose input, for the GPIO function.
1
Pin is configured as general-purpose output, for the GPIO function.
88
6
5
0
0
PORT_PTCD field descriptions
6
5
0
0
PORT_PTADD field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
0
0
0
Description
4
3
PTADD
0
0
Description
2
1
PTCD
0
0
2
1
0
0
NXP Semiconductors
0
0
0
0
Advertisement
Table of Contents
