System Port B Pin Multiplexing Control Register: High (Sim_Muxptbh) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Address: 1800h base + 8h offset = 1808h
Bit 7
Read
MUXPTB3
Write
Reset
0
Field
7–6 Pin Mux Control
MUXPTB3
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
5–4 Pin Mux Control
MUXPTB2
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
3–2 Pin Mux Control
MUXPTB1
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
MUXPTB0 Pin Mux Control
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
9.8.10 System Port B Pin Multiplexing Control Register: High
(SIM_MUXPTBH)
Many of the I/O pins are shared with on-chip peripheral functions. This register selects
the multiplexing pin functions from ALT0 to ALT3. Default is ALT0 function, When the
Pin Muxing mode is configured for analog pins, all the digital functions on that pin are
disabled, including the pullup/output/input.
114
6 5
MUXPTB2
0 0
SIM_MUXPTBL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
MUXPTB1
0 0
Description
2 1
MUXPTB0
0 0
NXP Semiconductors
0
0