Table of Contents
Advertisement
Functional description
14.8.1.3 VREG
VDD
VREG
is a 1.8 V output regulator. It is the power supply for the digital logics such as
VDD
CPU and RAM.
14.8.1.4 VREG
VREFH
VREG
is a 3.7~4.9 V configurable output regulator. It is the reference voltage
VREFH
output for on-chip analog modules such as ADC.
This regulator can be enabled or disabled by configuring PMC_CTRL[VREFDN]. After
POR or enabled, the flag PMC_STAT[VREFRDY] is set, once the regulator output is
ready.
The regulator output voltage can be trimmed from 3.7 V to 4.9 V through the
PMC_VREFHCFG[T5V]. After reset, a factory trimmed value is automatically loaded to
the PMC_VREFHCFG register so that VREG
the write protection enable bit PMC_CTRL[GWREN] is set to 1, user can configure this
voltage to other levels according to the application need.
14.8.2 Power-on reset
The POR circuit monitors the VREG
VDD domain. When power is initially applied to the MCU, or when the supply voltage
drops below the V
POR
When POR reset occurs, the flag bit PMC_RST[PORF] is set to 1. This flag is not
affected by other system resets.
14.8.3 Low voltage reset (LVR)
The LVR circuit monitors the 5 V VREG
output (VDDF), and the 1.8 V VREG
generate a reset when detecting a low voltage condition on VDDX, VDDF or VDD1.8.
After an LVR reset occurs, the LVR system holds the MCU in reset status until the
supply voltage rises above the low voltage level.
230
outputs (VDD1.8), which represent the MCU
VDD
level, the POR circuit causes a reset condition.
VDDX
output (VDD1.8). The LVR circuit can
VDD
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
has a default output voltage. After
VREFH
output (VDDX), the 2.8 V VREG
VDDF
NXP Semiconductors
Advertisement
Table of Contents
