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IPC memory map and register descriptions
Field
0
Disables IPCE. Interrupt generated from the interrupt source is passed directly to CPU without
processing (bypass mode). The IPMPS register is not updated when the module is disabled.
1
Enables IPCE and interrupt generated from the interrupt source is processed by IPC before passing to
CPU.
6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
5
Pseudo Stack Empty
PSE
This bit indicates that the pseudo stack has no valid information. This bit is automatically updated after
each IPMPS register push or pull operation.
4
Pseudo Stack Full
PSF
This bit indicates that the pseudo stack register IPMPS register is full. It is automatically updated after
each IPMPS register push or pull operation. If additional interrupt is nested after this bit is set, the earliest
interrupt mask value(IPM0[1:0]) stacked in IPMPS will be lost.
0
IPMPS register is not full.
1
IPMPS register is full.
3
Pull IPM from IPMPS
PULIPM
This bit pulls stacked IPM value from IPMPS register to IPM bits of IPCSC. Zeros are shifted into bit
positions 1 and 0 of IPMPS.
0
No operation.
1
Writing 1 to this bit causes a 2-bit value from the interrupt priority mask pseudo stack register to be
pulled to the IPM bits of IPCSC to restore the previous IPM value.
2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
IPM
Interrupt Priority Mask
This field sets the mask for the interrupt priority control. If the interrupt priority controller is enabled, the
interrupt source with an interrupt level (ILRxx) value that is greater than or equal to the value of IPM will be
presented to the CPU. Writes to this field are allowed, but doing this will not push information to the
IPMPS register. Writing IPM with PULIPM setting when IPCE is already set, the IPM will restore the value
pulled from the IPMPS register, not the value written to the IPM register.
4.2.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
This register is used to store the previous interrupt priority mask level temporarily when
the currently active interrupt is executed.
Address: Eh base + 1h offset = Fh
Bit
7
Read
IPM3
Write
Reset
0
60
IPC_SC field descriptions (continued)
6
5
IPM2
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
IPM1
0
0
2
1
IPM0
0
0
NXP Semiconductors
0
0
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