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19.5.8.2
19.5.9
BDM mode.....................................................................................................................................................339
19.6
Reset overview..............................................................................................................................................................339
19.7
FTM Interrupts..............................................................................................................................................................341
19.7.1
Timer overflow interrupt................................................................................................................................341
19.7.2
Channel (n) interrupt...................................................................................................................................... 341
20.1
Chip specific pules width timer.................................................................................................................................... 343
20.2
Introduction...................................................................................................................................................................344
20.2.1
Features.......................................................................................................................................................... 344
20.2.2
Modes of operation........................................................................................................................................ 344
20.2.3
Block diagram................................................................................................................................................ 345
20.3
External signal description............................................................................................................................................345
20.3.1
Overview........................................................................................................................................................ 345
20.3.2
PWTIN[3:0] - pulse width timer capture inputs..........................................................................................346
20.3.3
ALTCLK- alternative clock source for counter.......................................................................................... 346
20.4
Memory Map and Register Descriptions...................................................................................................................... 346
20.4.1
Pulse Width Timer Control and Status Register (PWTx_CS)....................................................................... 347
20.4.2
Pulse Width Timer Control Register (PWTx_CR)........................................................................................ 348
20.4.3
Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH)....................................................... 349
20.4.4
Pulse Width Timer Positive Pulse Width Register: Loq (PWTx_PPL)......................................................... 350
20.4.5
Pulse Width Timer Negative Pulse Width Register: High (PWTx_NPH).....................................................350
20.4.6
Pulse Width Timer Negative Pulse Width Register: Low (PWTx_NPL)...................................................... 351
20.4.7
Pulse Width Timer Counter Register: High (PWTx_CNTH)........................................................................ 351
20.4.8
Pulse Width Timer Counter Register: Low (PWTx_CNTL)......................................................................... 351
20.5
Functional description...................................................................................................................................................352
20.5.1
PWT counter and PWT clock pre-scaler........................................................................................................352
20.5.2
Edge detection and capture control................................................................................................................ 352
NXP Semiconductors
CnVH:L registers....................................................................................................................... 339
Chapter 20
Pules Width Timer (PWT)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
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