Debug Comparator C Low Register (Dbg_Ccl) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and registers

28.3.6 Debug Comparator C Low Register (DBG_CCL)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 5h offset = 18C5h
Bit 7
Read
Write
Reset
0
Field
CC[7:0] Comparator C Low
The Comparator C Low compare bits control whether Comparator C will compare the address bus bits
[7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
28.3.7 Debug FIFO High Register (DBG_FH)
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 6h offset = 18C6h
Bit 7
Read
Write
Reset
0
556
NOTE
6 5
0 0
DBG_CCL field descriptions
NOTE
6 5
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
CC[7:0]
0 0
Description
4 3
F[15:8]
0 0
2 1
0 0
2 1
0 0
NXP Semiconductors
0
0
0
0