Limit Cmp Bias Register (Gdu_Sigbias) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
0 A voltage over 22 V is not detected.
1 A voltage over 22 V is detected.
6 Overvoltage Protection 24 V
OVP24V
This bit is set when a voltage over 24 V is detected. The bit is cleared by writing a logic 1 to it.
0 A voltage over 24 V is not detected.
1 A voltage over 24 V is detected.
5–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
PHASE GDU Phase status
0 Phase detector comparator is in disable mode or in the enable mode and INP < INM - (absolute value
of input offset)
1 Phase detector comparator is in enable mode and INP > INM + (absolute value of input offset)

25.6.28 LIMIT CMP BIAS Register (GDU_SIGBIAS)

In Scan mode, safe protection should be applied.
Address: 20h base + 185Fh offset = 187Fh
Bit 7
Read
BIASSEL
Write
Reset
0
Field
7 Current sensor Bias Voltage Selection bit
BIASSEL
NOTE: PMC V
0 Bias voltage selected from V
1 Bias voltage selected from V
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
25.7 Functional description
NXP Semiconductors
GDU_STATREG field descriptions (continued)
6 5
0 0
GDU_SIGBIAS field descriptions
is disabled by default. Customer must connect external V
REFH
V regulator.
REFH
REFH
.
DDX
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NOTE
4 3
0
0 0
Description
.
Chapter 25 Gate Drive Unit (GDU)
2 1
0 0
or enable internal
REFH
0
0
461