Phcmp1 Status And Control Register (Gdu_Phcmp1Scr) - NXP Semiconductors MC9S08SU16 Reference Manual

25.6.8 PHCMP1 Status and Control Register (GDU_PHCMP1SCR)

Address: 20h base + 7h offset = 27h
Bit 7
Read 0
Write
Reset 0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
3 Comparator Interrupt Enable Falling
IEF
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
2 Analog Comparator Flag Rising
CFR
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit.
0 Rising edge on COUT has not been detected.
1 Rising edge on COUT has occurred.
1 Analog Comparator Flag Falling
CFF
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit.
0 Falling edge on COUT has not been detected.
1 Falling edge on COUT has occurred.
0 Analog Comparator Output
COUT
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
NXP Semiconductors
6 5
0
IER
0 0
GDU_PHCMP1SCR field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
CFR
IEF
w1c
0 0
Description
Chapter 25 Gate Drive Unit (GDU)
2 1
CFF COUT
w1c
0 0
0
0
445