NXP Semiconductors MC9S08SU16 Reference Manual page 56

Interrupts
• Interrupt priority mask can be modified during main flow or interrupt service
execution.
• Previous interrupt mask level is automatically stored when interrupt vector is fetched
(four levels of previous values accommodated)
Inputs
INTIN0
INTIN1
.
.
.
INTIN47
ILR Register Content
ILR0
x
x
x
x
.
x
.
x
x
.
x
x
x
x
x
x
x
ILR47
x
Figure 4-2. Interrupt priority controller block diagram
The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts
with programmable priority levels. This module also allows implementation of
preemptive interrupt according to the programmed interrupt priority with minimal
software overhead. The IPC consists of three major functional blocks:
56
ILR0[1:0]
ILR1[1:0]
.
.
.
ILR47[1:0]
x
x
x
x
Stop
x 1 0
x
x
x
00
x
IPCE
x
x (IPC Enable)
x
x
x
x
DECODE
AND SHIFT
LOGIC
[1 :0]
6
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
+
+
. .
. .
. .
+
IPMPS
(Interrupt Priority Mask Pseudo Stack Register)
IPM
[1:0] [1:0] [1:0]
Two bits are pushed during vector fetch
Two bits are pulled by
software (PULIPM = 1)
ADDRESS[5:0]
VFETCH
Outputs
INTOUT0
INTOUT1
INTOUT47
CPU
[1:0]
NXP Semiconductors