Table of Contents
Advertisement
Module functional categories
Table 2-1. Module functional categories (continued)
Module category
Clocks
Security
Analog
Timers
Communications
Human-Machine Interfaces (HMI)
2.2.1 S08L core modules
The following core modules are available on this device.
Module
HCS08 V6 CPU
Debug module
2.2.2 System modules
The following system modules are available on this device.
36
• Up to 768 bytes SRAM, including 256 B of which is unrestricted, and the rest
512 B is restricted during flash erasing and programming.
• Up to 8 bytes system register file
• Internal clock source
• 31.25 to 39.0625 kHz IRC
• 20 kHz oscillator with functional in all power modes
• Frequency-locked loop
• DC to 40 MHz
• Windowed COP watchdog
• One cyclic redundancy check (CRC)
• Two 12-bit analog-to-digital converters (ADC)
• One high speed comparator (CMP) with internal 6-bit digital-to-analog
converter (DAC)
• One gate drive unit (GDU)
• One 16-bit PWM
• One 16-bit FTM
• One 16-bit modulo timer (MTIM)
• Two pulse width timers (PWT)
• One programmable delay block (PDB)
• One inter-integrated circuit (I
• One serial communications interface (SCI)
• Port control (PORT)
• One keyboard interrupt (KBI)
Table 2-2. Core modules
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08
CPU. Several instructions and enhanced addressing modes were added to
improve C compiler efficiency and to support a new background debug system
which replaces the monitor mode of earlier M68HC08 microcontrollers.
The DBG module implements an on-chip ICE (in-circuit emulation) system and
allows non-intrusive debug of application software by providing an on-chip trace
buffer with flexible triggering capability. The trigger can also provide extended
breakpoint capacity. The on-chip ICE system is optimized for the HCS08 8-bit
architecture and supports 64 KB of memory space.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
2
C) module
Description
NXP Semiconductors
Advertisement
Table of Contents
