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N
Tx
Y
Last byte
transmitted?
N
N
RXAK=0?
Y
End of
Y
address cycle
(master Rx)?
N
Write next
byte to Data reg
Switch to
Rx mode
Generate stop
Dummy read
signal (MST=0)
from Data reg
Notes:
1. If general call is enabled, check to determine if the received address is a general call address (0x00).
If the received address is a general call address, the general call must be handled by user software.
2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address.
Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer.
NXP Semiconductors
Entry of ISR
Clear STARTF
Clear IICIF
Log Start Count++
Is this a Repeated-START
(Start Count > 1)?
Y
Y
Rx
Tx/Rx?
Y
Last byte
to be read?
N
Y
2nd to
last byte to be
read?
N
Generate stop
Set TXAK
signal (MST=0)
Read data from
Data reg
and store
Figure 21-5. Typical I2C interrupt routine
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
Is STOPF
set?
N
Y
Is STARTF
set?
N
Clear IICIF
N
Master
mode?
Clear ARBL
N
IAAS=1?
Y
Address transfer
Multiple
N
addresses?
Y
Read Address from
Data register
and store
Y (read)
SRW=1?
N (write)
Set Tx mode
Write data
to Data reg
Set Rx mode
Dummy read
from Data reg
RTI
Y
Clear STOPF
Clear IICIF
Zero Start Count
Y
Arbitration
lost?
N
Y
IAAS=1?
Data transfer
N
see note 2
see note 1
Rx
Tx/Rx?
Tx
Y
ACK from
receiver?
N
Read data from
Transmit
Data reg
next byte
and store
Switch to
Rx mode
Dummy read
from Data reg
393
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