Introduction - NXP Semiconductors MC9S08SU16 Reference Manual

Introduction

23.2 Introduction
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, to the hardware trigger inputs of ADCs and/or generates
the interval triggers to DACs, so that the precise timing between ADC conversions and/or
DAC updates can be achieved.
23.3 Features
The PDB has the following features:
• 16-bit resolution with a shared prescaler
• Support software and hardware trigger
• Support continuous count mode or single shot delay mode
• Supply on-fly delay value update
• Selective output mode: logic level or one-shot pulse
23.4 Block diagram
The following figure show the block diagram of the PDB.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors