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Initialization/application information
In FBELP and FBILP modes, the FLL is not on so that lock detect function is not
applicable.
12.4.7.2 External reference clock monitor
In FBE, FEE, or FBELP modes, if 1 is written to ICS_C4[CME], the clock monitor is
enabled. If the external reference falls below a certain frequency, the MCU will reset.
The SIM_SRS[LOC] will be set to indicate the error.
12.5 Initialization/application information
This section provides example code to give some basic direction to a user on how to
initialize and configure the ICS module. The example software is implemented in C
language.
12.5.1 Initializing FEI mode
The following code segment demonstrates setting ICS to FEI mode.
Example: 12.5.1.1 FEI mode initialization routine
/* the following code segment demonstrates setting the ICS to FEI mode using the factory
trim value. The resulting ICSOUT frequency is fint_ft*1024/BDIV. */
ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured
ICS_C1 = 0x04; // internal reference clock as source to FLL
while ((ICS_S & ICS_S_LOCK_MASK) == 0); // wait for FLL to lock
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies
/* the following code segment demonstrates setting the ICS to FEI mode using a custom trim
value provided by a programming tool. The resulting ICSOUT frequency is fint_t*1024/BDIV. */
ICS_C3 = *((uint8_t*) 0xFF6F); // trim internal reference clock
ICS_C4 = *((uint8_t*) 0xFF6E); // fine trim internal reference clock
ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured
ICS_C1 = 0x04; // internal reference clock as source to FLL
while ((ICS_S & ICS_S_LOCK_MASK) == 0); // wait for FLL to lock
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies
12.5.2 Initializing FBI mode
The following code segment demonstrates setting ICS to FBI mode.
Example: 12.5.2.1 FBI mode initialization routine
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
202
NXP Semiconductors
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