Ipc Memory Map And Register Descriptions; Ipc Status And Control Register (Ipc_Sc) - NXP Semiconductors MC9S08SU16 Reference Manual

• The IPM is automatically updated to the level the interrupt is servicing and the
original level is kept in IPMPS. Watch out for the full (PSF) bit if nesting for more
than four levels is expected.
• Before leaving the interrupt service routine, the previous levels must be restored
manually by setting PULIPM bit. Watch out for the full (PSF) bit and empty (PSE)
bit.
4.2

IPC memory map and register descriptions

Absolute
address
(hex)
E

IPC Status and Control Register (IPC_SC)

F Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
1860 Interrupt Level Setting Registers n (IPC_ILRS0)
1861 Interrupt Level Setting Registers n (IPC_ILRS1)
1862 Interrupt Level Setting Registers n (IPC_ILRS2)
1863 Interrupt Level Setting Registers n (IPC_ILRS3)
1864 Interrupt Level Setting Registers n (IPC_ILRS4)
1865 Interrupt Level Setting Registers n (IPC_ILRS5)
1866 Interrupt Level Setting Registers n (IPC_ILRS6)
1867 Interrupt Level Setting Registers n (IPC_ILRS7)
4.2.1 IPC Status and Control Register (IPC_SC)
This register contains status and control bits for the IPC.
Address: Eh base + 0h offset = Eh
Bit 7
Read
IPCE
Write
Reset 0
Field
7 Interrupt Priority Controller Enable
IPCE
This bit enables/disables the interrupt priority controller module.
NXP Semiconductors
IPC memory map
Register name
6 5
0 PSE PSF
0 1
IPC_SC field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
(in bits)
8 R/W
8
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
4 3
0
PULIPM
0 0
Description
Chapter 4 Interrupt
Section/
Reset value
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2 1
0
IPM
0 0
0
0
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