System Por Register (Sim_Porregn) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
0 Same as ICSOUTCLK.
1 ICSOUTCLK divides by 2.
4–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 Clock 2 output divider value
DIV2
This field sets the divide value for the bus/flash, follow DIV1.
NOTE: The bus clock max speed is 20 MHz. When CPU clock is up to 40 MHz, CPU:Bus could not be
0 Not divided from divider1.
1 Divide by 2 from divider1.
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Clock 3 output divider value
DIV3
This field sets the divide value for the PDB/PWM.
0 Same as ICSOUTCLK.
1 ICSOUTCLK divides by 2.

9.8.16 System POR Register (SIM_PORREGn)

Address: 1800h base + 10h offset + (1d × i), where i=0d to 7d
Bit 7
Read
Write
Reset 0
Field
PORREG Power-on-reset only registers
These 8 byte registers can only be reset by power-on.
NXP Semiconductors
SIM_SCDIV field descriptions (continued)
1:1,but only 2:1.
6 5
0 0
SIM_PORREGn field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
Description
4 3
PORREG
0 0
Description
2 1
0 0
0
0
121