Limit1 Dac Control Register (Gdu_Limit1Daccr) - NXP Semiconductors MC9S08SU16 Reference Manual

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Memory map and register definition
Field
0
Falling edge on COUT is not detected.
1
Falling edge on COUT occurs.
0
Analog Comparator Output
COUT
Reading the COUT bit returns the current value of the analog comparator output. This bit is reset to 0 and
reads as VCR1[INV] when the Analog Comparator module is disabled (VCR1[EN] = 0). Writing to this bit
has no effect.

25.6.26 LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)

Address: 20h base + 185Dh offset = 187Dh
Bit
7
Read
0
Write
Reset
0
Field
7–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
VOSEL
DAC Output Voltage Select
This field selects an output voltage from one of the 64 distinct levels.
DACO = (V
25.6.27 PDCS and Clamp Status Register (GDU_STATREG)
Address: 20h base + 185Eh offset = 187Eh
Bit
7
Read
OVP22V
Write
w1c
Reset
0
Field
7
Overvoltage Protection 22 V
OVP22V
This bit is set when a voltage over 22 V is detected. The bit is cleared by writing a logic 1 to it.
460
GDU_LIMIT1SCR field descriptions (continued)
6
5
0
0
GDU_LIMIT1DACCR field descriptions
/64) × (VOSEL[5:0] + 1), so the DACO range is from V
DDX
6
5
OVP24V
w1c
0
0
GDU_STATREG field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
VOSEL
0
0
Description
DDX
4
3
0
0
0
Description
2
1
0
0
/64 to V
.
DDX
2
1
PHASE
0
0
NXP Semiconductors
0
0
0
0

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