Pwm Disable Mapping Registers 1: Low (Pwm_Dmap1L) - NXP Semiconductors MC9S08SU16 Reference Manual

Deadtime is affected by changes to the prescaler value. The
deadtime duration is determined as follows: DT = P × PWMDT
– 1, where DT is deadtime, P is the prescaler value, PWMDT is
the programmed value of dead time. For example: if the
prescaler is programmed for a divide-by-two and PWMDT is
set to five, then P = 2 and the deadtime value is equal to DT = 2
× 5 – 1 = 9 PWM clock cycles. A special case exists when the P
= 1, DT = PWMDT
The PWMDT field is used to control the deadtime during transitions of the even PWM
output.
Address: 40h base + 19h offset + (2d × i), where i=0d to 1d
Bit 7
Read
Write
Reset 0
Field
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
PWMDT11_8 PWM Pulse Width Value7:0

26.4.17 PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)

These write-protectable registers determine which PWM pins are affected by the fault
protection inputs. Reset sets all of the bits used in the PWM disable mapping registers.
These registers are write protected after the WP bit in the PWM configure register is set.
Reserved bits 15-8 in the DMAP2 register cannot be modified. The bits are read as zero.
Address: 40h base + 1Ch offset = 5Ch
Bit 7
Read
Write
Reset
1
Field
DISMAP7_0 PWM Disable Mapping7:0
NXP Semiconductors
NOTE
6 5
0
0 0
PWM_DTIMnH field descriptions
6 5
1 1
PWM_DMAP1L field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
4 3
0 1
Description
4 3
DISMAP7_0
1 1
Description
2 1
PWMDT11_8
1 1
2 1
1 1
0
1
0
1
519