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When PMC_TPTM[TRMTPEN] is set, the HTDS flag assert/de-assert threshold is
defined by the TOT[3:0] bits in the same register. For the detailed HTDS flag assert/de-
assert thresholds, see the reference in TOT[3:0].
Before configuring the TOT[3:0] bits, user should set PMC_CTRL[GWREN] to unlock
the write protection.
14.8.7 Low-power RC oscillator
PMC integrates a low-power RC oscillator (LPO) which provides a typical 20 kHz
output. This LPO can serve as an independent clock source for the MCU on-chip
modules such as watchdog.
This RC oscillator is set to ON by default in the FPM mode, and can be controlled to
OFF in the RPM mode by configuring PMC_CTRL[RC20KENSTP].
The RC oscillator out frequency can be configured by user through the OSCOT[5:0] bits
in PMC_RC20KTRM register. Before writing to OSCOT[5:0], user should set
PMC_CTRL[GWREN].
14.9 Application information
1. VREFH readiness
VREFH is a high-accuracy voltage reference. It needs 3 ms to be stable after
PMC_STAT[VREFRDY] is asserted. When entering the Stop mode, VREFH is
disabled automatically. So after exiting from the Stop mode, it requires to wait
enough settling time. After the PMC_VREFHCFG setting is changed, it takes some
time to get it settled. ADC or other functions using VREFH cannot work correctly
during this transition period.
2. 20 kHz LPO calibration
LPO has to be calibrated after the PMC powers up, in order to get the ±5% precision.
The LPO clock is connected to SBAR (in the SIM module), and the calibration can
be achieved by using FTM1 with on-chip clock. Refer to the SIM chapter for more
detailed setting information.
3. Special write enable register handling
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 14 Power Management Controller (PMC)
233
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