System Management Bus Specification - NXP Semiconductors MC9S08SU16 Reference Manual

Functional description
• AD[7:1] in Address Register 1, which contains the I2C primary slave address, always
participates in the address matching process. It provides a 7-bit address.
• If the ADEXT bit is set, AD[10:8] in Control Register 2 participates in the address
matching process. It extends the I2C primary slave address to a 10-bit address.
Additional conditions that affect address matching include:
• If the GCAEN bit is set, general call participates the address matching process.
• If the ALERTEN bit is set, alert response participates the address matching process.
• If the SIICAEN bit is set, Address Register 2 participates in the address matching
process.
• If the RMEN bit is set, when the Range Address register is programmed to a nonzero
value, any address within the range of values of Address Register 1 (excluded) and
the Range Address register (included) participates in the address matching process.
The Range Address register must be programmed to a value greater than the value of
Address Register 1.
When the I2C module responds to one of these addresses, it acts as a slave-receiver and
the IAAS bit is set after the address cycle. Software must read the Data register after the
first byte transfer to determine that the address is matched.

21.5.4 System management bus specification

SMBus provides a control bus for system and power management related tasks. A system
can use SMBus to pass messages to and from devices instead of tripping individual
control lines.
Removing the individual control lines reduces pin count. Accepting messages ensures
future expandability. With the system management bus, a device can provide
manufacturer information, tell the system what its model/part number is, save its state for
a suspend event, report different types of errors, accept control parameters, and return its
status.
21.5.4.1 Timeouts
The T parameter allows a master or slave to conclude that a defective device
TIMEOUT,MIN
is holding the clock low indefinitely or a master is intentionally trying to drive devices
off the bus. The slave device must release the bus (stop driving the bus and let SCL and
SDA float high) when it detects any single clock held low longer than T
Devices that have detected this condition must reset their communication and be able to
receive a new START condition within the timeframe of T
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
TIMEOUT,MIN
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TIMEOUT,MAX
NXP Semiconductors
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