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9.8.5
System Options Register 1 (SIM_SOPT1).................................................................................................... 108
9.8.6
System Options Register 2 (SIM_SOPT2).................................................................................................... 110
9.8.7
System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)............................................... 111
9.8.8
System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH).............................................. 112
9.8.9
System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)............................................... 113
9.8.10
System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH).............................................. 114
9.8.11
System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)............................................... 116
9.8.12
System Clock Gating Control 1 Register (SIM_SCGC1)..............................................................................116
9.8.13
System Clock Gating Control 2 Register (SIM_SCGC2)..............................................................................117
9.8.14
System Clock Gating Control 3 Register (SIM_SCGC3)..............................................................................119
9.8.15
System Clock Divider Register (SIM_SCDIV)............................................................................................. 120
9.8.16
System POR Register (SIM_PORREGn)...................................................................................................... 121
9.8.17
Illegal Address Register: High (SIM_ILLAH).............................................................................................. 122
9.8.18
Illegal Address Register: Low (SIM_ILLAL)............................................................................................... 122
9.8.19
Universally Unique Identifier Register 0 (SIM_UUID0).............................................................................. 123
9.8.20
Universally Unique Identifier Register 1 (SIM_UUID1).............................................................................. 123
9.8.21
Universally Unique Identifier Register 2 (SIM_UUID2).............................................................................. 124
9.8.22
Universally Unique Identifier Register 3 (SIM_UUID3).............................................................................. 124
9.8.23
Universally Unique Identifier Register 4 (SIM_UUID4).............................................................................. 125
9.8.24
Universally Unique Identifier Register 5 (SIM_UUID5).............................................................................. 125
9.8.25
Universally Unique Identifier Register 6 (SIM_UUID6).............................................................................. 126
9.8.26
Universally Unique Identifier Register 7 (SIM_UUID7).............................................................................. 126
10.1
Introduction...................................................................................................................................................................127
10.1.1
Features.......................................................................................................................................................... 127
10.2
Programmer's Model and CPU Registers..................................................................................................................... 128
10.2.1
Accumulator (A)............................................................................................................................................ 128
10.2.2
Index Register (H:X)......................................................................................................................................129
NXP Semiconductors
Title
Chapter 10
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Page
7
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