Interrupts - NXP Semiconductors MC9S08SU16 Reference Manual

2. The 16-bit buffer of PWT counter is reset and the reading coherency mechanism is
restarted
3. The PWT clock pre-scaler output is reset
4. The edge detection logic is reset
5. The capture logic is reset and the latching mechanism of pulse width registers is also
restarted.
6. PWTxPPH, PWTxPPL, PWTxNPH, PWTxNPL are set to 0x00
7. PWTOV, PWTRDY, TGL and LVL status are set to 0
8. All other PWT register settings are not changed
Writing a 0 to PWTEN bit also has the above effects except that the reset state will be
held until the PWTEN bit is set to 1.
20.7

Interrupts

20.7.1 Description of interrupt operation
The other major component of the PWT is the interrupts control logic. When the
PWTOV bit and POVIE bit of PWTxCS are set, a PWT overflow interrupt can be
generated. When PWTRDY bit and PRDYIE bit of PWTxCS are set, a pulse width data
ready interrupt can be generated. The PWTIE bit of PWTxCS controls the interrupt
generation of the PWT module. The functionality of the PWT is not affected while the
interrupt is being generated.
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 20 Pules Width Timer (PWT)
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