Generator Loading - NXP Semiconductors MC9S08SU16 Reference Manual

26.3.8

Generator loading

26.3.8.1 Load enable
The load okay (LDOK) bit enables loading the PWM generator with:
• A prescaler divisor from the PRSC1 and PRSC0 bits in the control (CTRL) register
• A PWM period from the PWM counter modulus (CMOD) register
• A PWM pulse width from the all PWM value (VALn) registers
LDOK prevents reloading of these PWM parameters simultaneously. Setting LDOK
allows the prescale bits, CMOD and VALn registers to be loaded into a set of buffers.
The loaded buffers are used by the PWM generator at the beginning of the next PWM
reload cycle. Set LDOK by reading it, and then writing a 1 to it. After loading, LDOK is
automatically cleared.
26.3.8.2 Load frequency
The LDFQ3, LDFQ2, LDFQ1, and LDFQ0 bits in the CTRL register select an integral
loading frequency of one to 16-PWM reload opportunities. The LDFQ bits take effect at
every PWM reload opportunity, regardless of the state of the LDOK bit. The HALF bit in
the CTRL register controls half-cycle reloads for center-aligned PWMs. If the HALF bit
is set, a reload opportunity occurs at both beginning of the PWM cycle and at the PWM
half cycle. If the HALF bit is not set, a reload opportunity occurs only at the beginning of
the cycle. Reload opportunities can only occur at the beginning of a PWM cycle in edge-
aligned mode.
Loading a new modulus on a half cycle will force the counter to
the new modulus value minus one count on the next PWM
clock cycle. Half cycle reloads are only changes reload rate in
center-aligned mode. Enabling or disabling half cycle reloads in
edge-aligned mode will have no effect on the reload rate.
Up/Down
Counter
Reload
Change
Reload
Frequency
NXP Semiconductors
To Every
Two Opportunities
Figure 26-18. Full cycle reload frequency change
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
NOTE
To Every
Four Opportunities
To Every
Opportunity
497