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Functional description
12.4.2 Mode switching
ICS_C1[IREFS] can be changed at anytime, but the actual switch to the newly selected
clock is shown by ICS_S[IREFST]. When switching between FLL engaged internal (FEI)
and FLL engaged external (FEE) modes, the FLL begins locking again after the switch is
completed.
ICS_C1[CLKS] can also be changed at anytime, but the actual switch to the newly
selected clock is shown by ICS_S[CLKST]. If the newly selected clock is not available,
the previous clock remains selected.
When mode switching is from FEE, FBE or FBELP to FEI, it is
suggested to wait IREFST switch completion, then change
ICS_C1[CLKS].
12.4.3 Bus frequency divider
ICS_C2[BDIV] can be changed anytime and the actual switch to the new frequency
occurs immediately.
12.4.4 Low-power field usage
The Low-Power (LP) field in the ICS_C2 register is provided to allow the FLL to be
disabled and thus conserve power when it is not being used.
However, in some applications it may be desirable to allow the FLL to be enabled and to
lock for maximum accuracy before switching to an FLL engaged mode. To do this, write
0b to ICS_C2[LP].
12.4.5 Internal reference clock
When ICS_C1[IRCLKEN] is set, the internal reference clock signal is presented as
ICSIRCLK, which can be used as an additional clock source. To re-target the ICSIRCLK
frequency, write a new value to the ICS_C3[SCTRIM] bits to trim the period of the
internal reference clock:
• Writing a larger value slows down the ICSIRCLK frequency.
• Writing a smaller value to the ICS_C3 register speeds up the ICSIRCLK frequency.
The trim bits affect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI),
FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode.
200
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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