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6.2.2 Wait mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT
instruction, the CPU enters a low-power state in which it is not clocked. The
CCR
[I] is
cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt
request occurs, the CPU exits the wait mode and resumes processing, beginning with the
stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug
commands can be used. Only the BACKGROUND command and memory-access-with-
status commands are available when the MCU is in wait mode. The memory-access-with-
status commands do not allow memory access, but they report an error indicating that the
MCU is in either stop or wait mode. The BACKGROUND command can be used to
wake the MCU from wait mode and enter active background mode.
6.2.3 Stop mode
To enter stop, the user must execute a STOP instruction with stop mode enabled
(SIM_SOPT1[STOPE] = 1). The ICS enters its standby state, as does the voltage
regulator and the ADC. The states of all of the internal registers and logic, as well as the
RAM content, are maintained. The I/O pin states are not latched at the pin. Instead they
are maintained by virtue of the states of the internal logic driving the pins being
maintained.
Exit from stop is done by asserting reset or through an interrupt. The interrupt include the
asynchronous interrupt from the IRQ or KBI pins or ADC, CMP, I2C, SCI.
If stop is exited by means of the RESET pin, then the MCU will be reset and operation
will resume after taking the reset vector. Exit by means of an asynchronous interrupt or
the real-time interrupt will result in the MCU taking the appropriate interrupt vector.
Both low voltage detection and low reset are disabled in stop mode.
6.2.4 Active BDM enabled in stop mode
Entry into the active background mode from run mode is enabled if the
BDC_SCR[ENBDM] bit is set. This register is described in the
development
support. If
BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
72
NXP Semiconductors
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