Pwm Output Control Register: Low (Pwm_Outl) - NXP Semiconductors MC9S08SU16 Reference Manual

26.4.7 PWM Output Control Register: Low (PWM_OUTL)

Address: 40h base + 6h offset = 46h
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 Output 5
OUT5
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM5 is inactive
1 PWM5 is complement of PWM 4 (complementary channel operation); PWM5 is active (independent
channel operation)
4 Output 4
OUT4
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM4 is inactive
1 PWM4 is active
3 Output 3
OUT3
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM3 is inactive
1 PWM3 is complement of PWM2 (complementary channel operation); PWM3 is active (independent
channel operation)
2 Output 2
OUT2
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM2 is inactive
1 PWM2 is active
1 Output 1
OUT1
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM1 is inactive
1 PWM1 is complement of PWM0 (complementary channel operation); PWM1 is active (independent
channel operation)
0 Output 0
OUT0
When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins.
0 PWM0 is inactive
1 PWM0 is active
NXP Semiconductors
6 5
OUT5 OUT4
0 0
PWM_OUTL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
4 3
OUT3 OUT2
0 0
Description
2 1
OUT1 OUT0
0 0
0
0
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