Initialization/Application Information - NXP Semiconductors MC9S08SU16 Reference Manual

ACK phase, the bus is released to accept the next byte if the master can send the
clock immediately.
• On the slave side, two-times writes to the I2C_D buffer may be limited by the
master's clock and START/repeated-START signal. This is not currently supported,
and the master's START/repeated-START signal will break data transfers. To release
the bus, do a dummy read or write to the I2C_D buffer again. It is suggested to send
repeated-START/START during intervals as before.
• The master receive should send a NACK in the next-to-last ISR, if it wants to do the
STOP or the repeated-START work. The transmitting slave which receives the
NACK, will switch to receive mode, and do a dummy read to release SCL and SDA
signals.

21.6 Initialization/application information

Module Initialization (Slave)
1. Write: Control Register 2
• to enable or disable general call
• to select 10-bit or 7-bit addressing mode
2. Write: Address Register 1 to set the slave address
3. Write: Control Register 1 to enable the I2C module and interrupts
4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
5. Initialize RAM variables used to achieve the routine shown in the following figure
Module Initialization (Master)
1. Write: Frequency Divider register to set the I2C baud rate (see example in
description of ICR)
2. Write: Control Register 1 to enable the I2C module and interrupts
3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4. Initialize RAM variables used to achieve the routine shown in the following figure
5. Write: Control Register 1 to enable TX
6. Write: Control Register 1 to enable MST (master mode)
7. Write: Data register with the address of the target slave (the LSB of this byte
determines whether the communication is master receive or transmit)
The routine shown in the following figure encompasses both master and slave I2C
operations. For slave operation, an incoming I2C message that contains the proper
address begins I2C communication. For master operation, communication must be
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
391