Table of Contents
Advertisement
Functional description
When polling is used, this sequence is naturally satisfied in the normal course of the user
program. If hardware interrupts are used, SCI_S1 must be read in the interrupt service
routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the
sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the
RxD line remains idle for an extended period of time. IDLE is cleared by reading SCI_S1
while SCI_S1[IDLE] is set and then reading SCI_D. After SCI_S1[IDLE] has been
cleared, it cannot become set again until the receiver has received at least one new
character and has set SCI_S1[RDRF].
If the associated error was detected in the received character that caused SCI_S1[RDRF]
to be set, the error flags - noise flag (SCI_S1[NF]), framing error (SCI_S1[FE]), and
parity error flag (SCI_S1[PF]) - are set at the same time as SCI_S1[RDRF]. These flags
are not set in overrun cases.
If SCI_S1[RDRF] was already set when a new character is ready to be transferred from
the receive shifter to the receive data buffer, the overrun (SCI_S1[OR]) flag is set instead
of the data along with any associated NF, FE, or PF condition is lost.
At any time, an active edge on the RxD serial data input pin causes the
SCI_S2[RXEDGIF] flag to set. The SCI_S2[RXEDGIF] flag is cleared by writing a 1 to
it. This function depends on the receiver being enabled (SCI_C2[RE] = 1).
22.5.5 Baud rate tolerance
A transmitting device may operate at a baud rate below or above that of the receiver.
Accumulated bit time misalignment can cause one of the three stop bit data samples
(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the
RT8, RT9, and RT10 samples are not all the same logical values. A framing error will
occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9,
and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid
falling edge within the frame. Resynchronization within frames will correct a
misalignment between transmitter bit times and receiver bit times.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
416
NXP Semiconductors
Advertisement
Table of Contents
