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On-chip debug system (DBG)
A AND B Data (Full Mode) ̶ This is called a full mode because address, data, and R/W
(optionally) must match within the same bus cycle to cause a trigger event. Comparator A
checks address, the low byte of comparator B checks data, and R/W is checked against
RWA if RWAEN = 1. The high-order half of comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN =
TAG = 1), but if you do, the comparator B data match is ignored for the purpose of
issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator
A address matches.
A AND NOT B Data (Full Mode) ̶ Address must match comparator A, data must not
match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All
three conditions must be met within the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN =
TAG = 1), but if you do, the comparator B data match is ignored for the purpose of
issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator
A address matches.
Event-Only B (Store Data) ̶ Trigger events occur each time the address matches the
value in comparator B. Trigger events cause the data to be captured into the FIFO. The
debug run ends when the FIFO becomes full.
A Then Event-Only B (Store Data) ̶ After the address has matched the value in
comparator A, a trigger event occurs each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run
ends when the FIFO becomes full.
Inside Range (A ≤ Address ≤ B) ̶ A trigger occurs when the address is greater than or
equal to the value in comparator A and less than or equal to the value in comparator B at
the same time.
Outside Range (Address < A or Address > B) ̶ A trigger occurs when the address is
either less than the value in comparator A or greater than the value in comparator B.
27.3.6 Hardware breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger
conditions described in
Trigger modes
to be used to generate a hardware breakpoint
request to the CPU. TAG in DBGC controls whether the breakpoint request will be
treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the
current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
542
NXP Semiconductors
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