Deadtime Generators - NXP Semiconductors MC9S08SU16 Reference Manual

26.3.4 Deadtime generators

While in the complementary mode, each PWM pair can be used to drive top/bottom
transistors. Ideally, the PWM pairs are an inversion of each other. When the top PWM
channel is active, the bottom PWM channel is inactive and vice versa.
To avoid short-circuiting between top and bottom transistor, there must be no overlap of
conducting intervals between top and bottom transistor. But the transistor's
characteristics make its switching-off time longer than switching-on time. To avoid the
conducting overlap of top and bottom transistors, deadtime may be operationally inserted
in the switching period.
Deadtime generators automatically insert software-selectable activation delays into each
pair of PWM outputs during switching. The PWM deadtime (DTIM) registers specify the
number of PWM clock cycles to use for deadtime delay. Every time the PWM generator
output changes state, deadtime is inserted. DTIM controls deadtime during both low state
to high state transitions and high state to low state transitions. Deadtime forces both
PWM outputs in the pair to the inactive state.
PWM
Generator
The following figures illustrate deadtime insertion in different operation conditions.
NXP Semiconductors
OUT0
MUX
PWM0 &
PWM1
OUTCTL0
OUT2
MUX
Current
Status
PWM2 &
PWM3
OUTCTL2
OUT4
MUX
PWM4 &
PWM5
OUTCTL4
Figure 26-11. Deadtime generators
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Top/Bottom
OUT1
Generator
Deadtime
Generator
Top/Bottom
OUT3
Generator
Deadtime
Generator
Top/Bottom
OUT5
Generator
Deadtime
Generator
Top (PWM0)
Bottom (PWM1)
Top (PWM2)
Bottom (PWM3)
Top (PWM4)
Bottom (PWM5)
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