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Memory Map and Register Descriptions
Field
0
Output is asserted and de-asserted by input trigger or counter rollover.
1
Output a true high pulse.
4
PDB1 Counter Mode Enable
MOD1
0
Module is in single shot delay mode.
1
Module is in continuous count mode.
3
PDB0 Timer Compare Flag
TCF0
This bit is set when a successful compare occurs. Clear this bit by writing one to it.
2
PDB0 Timer Compare Interrupt Enable
TCIE0
0
Timer compare interrupt requests disabled.
1
Timer compare interrupt requests enabled.
1
PDB0 Trigger Output
TRGOUT0
Configure PDB0 trigger output as an pulse or level when a successful compare occurs.
0
Logic output mode, output is asserted and de-asserted by input trigger or counter rollover.
1
Pulse output mode, output a true high pulse.
0
PDB0 Counter Mode Enable
MOD0
0
Module is in single shot delay mode.
1
Module is in continuous count mode.
23.6.2 PDB Control Register 1 (PDB_CTRL1)
SWCLR0 and SWCLR1 are also used as PDB status bits to
indicate whether PDB0 and PDB1 are enabled or not.
Do NOT use BSET and BCLR instruction to this register,
which may cause unexpected software clear to SWCLR0 and
SWCLR1.
Address: 60h base + 1h offset = 61h
Bit
7
Read
CNTSEL1
Write
Reset
0
426
PDB_CTRL0 field descriptions (continued)
6
5
CNTSEL0
PRESCALER
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NOTE
4
3
SWCLR1
0
0
2
1
SWTRG1
SWCLR0
0
0
NXP Semiconductors
0
SWTRG0
0
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