Limit0 Cmp Status And Control Register (Gdu_Limit0Scr) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
FLTPER Filter sampling Period
When UCR1[SE] is equal to 0, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FLTPER to 0 disables the filter. For the filter programming and latency
details, see the Functional Description.
This field has no effect when UCR1[SE] is equal to 1. In that case, the external SAMPLE signal is used to
determine the sampling period.

25.6.20 LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR)

Address: 20h base + 1857h offset = 1877h
Bit 7
Read
Write
Reset 0
Field
7–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
The IER bit enables the CFR interrupt from the CMP. If this bit is set, an interrupt is asserted when the
CFR bit is set.
0 Interrupt is disabled.
1 Interrupt is enabled.
3 Comparator Interrupt Enable Falling
IEF
The IEF bit enables the CFF interrupt from the CMP. If this bit is set, an interrupt is asserted when the
CFF bit is set.
0 Interrupt is disabled.
1 Interrupt is enabled.
2 Analog Comparator Flag Rising
CFR
During normal operation, the CFR bit is set when a rising edge on COUT is detected. This bit is cleared by
writing a logic 1 to it.
0 Rising edge on COUT is not detected.
1 Rising edge on COUT occurs.
1 Analog Comparator Flag Falling
CFF
During normal operation, the CFF bit is set when a falling edge on COUT is detected. This bit is cleared by
writing a logic 1 to it.
NXP Semiconductors
GDU_LIMIT0FPR field descriptions
6 5
0
IER
0 0
GDU_LIMIT0SCR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
CFR
IEF
w1c
0 0
Description
Chapter 25 Gate Drive Unit (GDU)
2 1
CFF COUT
w1c
0 0
0
0
455