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Field
This field represents the number of consecutive samples that must agree, prior to the comparator output
filter accepting a new output state. For information regarding filter programming and latency, see the
Functional Description.
000
Filter is disabled. If SE = 1, then COUT is a logic 0 (this is not a legal state, and is not
recommended). If SE = 0, COUT = COUTA.
001
1 consecutive sample must agree (comparator output is simply sampled).
010
2 consecutive samples must agree.
011
3 consecutive samples must agree.
100
4 consecutive samples must agree.
101
5 consecutive samples must agree.
110
6 consecutive samples must agree.
111
7 consecutive samples must agree.
3–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Comparator hard block Hysteresis control
HYST
Defines the programmable hysteresis level. The hysteresis value associated with each level is device-
specific. See the device's data sheet for the exact values.
0
Level 0
1
Level 1
25.6.23 LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)
Address: 20h base + 185Ah offset = 187Ah
Bit
7
Read
SE
Write
Reset
0
Field
7
Sampling Enable
SE
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set
and WE is cleared. However, avoid writing 1 to both bits because this "11" case is reserved and may
change in future implementations.
NOTE: Set this bit to zero, because the sample input is connected to the logic 1.
0
Sampling mode is not selected.
1
Sampling mode is selected.
6
Windowing Enable
WE
NXP Semiconductors
GDU_LIMIT1CR0 field descriptions (continued)
6
5
0
WE
0
0
GDU_LIMIT1CR1 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
PMODE
INV
0
0
Description
Chapter 25 Gate Drive Unit (GDU)
2
1
COS
OPE
0
0
0
EN
0
457
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