Kbi Pin Enable Register (Kbi_Pe); Kbi Edge Select Register (Kbi_Es) - NXP Semiconductors MC9S08SU16 Reference Manual

15.5.2 KBI Pin Enable Register (KBI_PE)

KBI_PE contains the pin enable control bits.
Address: 7Ch base + 1h offset = 7Dh
Bit 7
Read
Write
Reset 0
Field
KBIPE KBI Pin Enables
Each of the KBIPEn bits enable the corresponding KBI interrupt pin.
0 Pin is not enabled as KBI interrupt.
1 Pin is enabled as KBI interrupt.

15.5.3 KBI Edge Select Register (KBI_ES)

KBI_ES contains the edge select control bits.
Address: 7Ch base + 2h offset = 7Eh
Bit 7
Read
Write
Reset
0
Field
KBEDG KBI Edge Selects
Each of the KBEDGn bits selects the falling edge/low-level or rising edge/high-level function of the
corresponding pin.
0 Falling edge/low level.
1 Rising edge/high level.
NXP Semiconductors
6 5
0 0
KBI_PE field descriptions
6 5
0 0
KBI_ES field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 15 Keyboard Interrupts (KBI)
4 3
KBIPE
0 0
Description
4 3
KBEDG
0 0
Description
2 1
0 0
2 1
0 0
0
0
0
0
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