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Memory Map and Register Descriptions
26.4.23 PWM Channel Control Register: High (PWM_CCTRLH)
This write-protectable register contains the configuration bits that determine PWM modes
of operation as detailed below. The ENHA bit cannot be modified after the WP bit in the
CNFG register is set. ENHA in turn provides protection for the VLMODE[1:0], SWP45,
SWP23 and SWP01 bits. The Mask bits are not write protectable.
Address: 40h base + 17E3h offset = 1823h
Bit
7
Read
ENHA
Write
Reset
0
Field
7
Enable Hardware Acceleration
ENHA
This bit enables writing to the VLMODE[1:0], SWP45, SWP23, and SWP01 bits. The bit is write protected
by the CNFG register WP bit.
0
Disable writing to VLMODE[1:0], SWP45, SWP23, and SWP01 bits
1
Enable writing to VLMODE[1:0], SWP45, SWP23, and SWP01 bits
6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 1.
MSK
Mask
These six bits determine the mask for each of the PWM logical channels.
0
Unmasked
1
Masked, channel set to a value of zero percent duty cycle
26.4.24 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)
This register is used to control PWM pulse generation for various applications, such as a
power-supply phase-shifting application.
The PECn bits only apply in edge-aligned operation during complementary mode. These
control bits allow the PWM pulses generated by both the odd and even VAL regs to be
XORed together prior to the complementary logic and deadtime insertion.
The PECn bits are buffered. The value written does not take
effect until the LDOK bit is set and the next PWM load cycle
begins. Reading PECn reads the value in a buffer and not
necessarily the value the PWM generator is currently using.
524
6
5
1
1
0
PWM_CCTRLH field descriptions
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
MSK
0
0
Description
2
1
0
0
NXP Semiconductors
0
0
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