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20 kHz low-power oscillator (LPO)
• Internal or external reference clocks can be used to control the FLL
• Reference divider is provided for external clock
• Internal reference clock has nine trim bits available
• Internal or external reference clocks can be selected as the clock source for the MCU
• Whichever clock is selected as the source can be divided down by 1, 2, 4, 8, 16, 32,
64 or 128
• FLL Engaged Internal mode is automatically selected out of reset
• A constant divide by 2 of the DCO output that can be select as BDC clock.
• Digitally-controlled oscillator (DCO) optimized for 32 MHz to 40 MHz frequency
range
• FLL lock detector and external clock monitor
• FLL lock detector with interrupt capability
• External reference clock monitor with reset capability
5.4 20 kHz low-power oscillator (LPO)
The 20 kHz low-power oscillator acts as a standalone low-frequency clock source in all
run, wait, and stop modes.
5.5 Peripheral clock gating
This device includes a clock gating system to manage the bus clock sources to the
individual peripherals. Using this system, the user can enable or disable the bus clock to
each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals
that are not in use, thereby reducing the overall run and wait mode currents.
For lowest possible run wait currents, user software must disable the clock source to any
peripheral not in use. The actual clock will be enabled or disabled immediately following
the write to the System Clock Gating Control registers (SIM_SCGCx, x=1, 2, 3). Any
peripheral with a gated clock cannot be used unless its clock is enabled. Writing to the
registers of a peripheral with a disabled clock has no effect.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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