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8.5.4
Port A Direction Register (PORT_PTADD)................................................................................................. 88
8.5.5
Port B Direction Register (PORT_PTBDD).................................................................................................. 89
8.5.6
Port C Direction Register (PORT_PTCDD).................................................................................................. 89
8.5.7
Port A Pullup Enable Register (PORT_PTAPE)........................................................................................... 90
8.5.8
Port B Pullup/Pulldown Enable Register (PORT_PTBPE)........................................................................... 91
8.5.9
Port C Pullup Enable Register (PORT_PTCPE)............................................................................................91
8.5.10
Port B High Drive Strength Selection Register (PORT_PTBHD)................................................................ 92
8.5.11
Port Clock Division Register (PORT_FCLKDIV)........................................................................................ 92
8.5.12
Port Filter Register 0 (PORT_IOFLT0).........................................................................................................93
8.5.13
Port Filter Register 1 (PORT_IOFLT1).........................................................................................................94
8.5.14
Port Filter Register 2 (PORT_IOFLT2).........................................................................................................95
9.1
Chip specific windowed COP.......................................................................................................................................97
9.2
System device identification (SDID)............................................................................................................................ 98
9.3
Universally unique identification (UUID).................................................................................................................... 98
9.4
Reset and system initialization......................................................................................................................................98
9.5
Computer operating properly (COP) watchdog............................................................................................................99
9.6
System options.............................................................................................................................................................. 100
9.6.1
BKGD pin...................................................................................................................................................... 100
9.6.2
RESET_b pin enable...................................................................................................................................... 101
9.7
System interconnection.................................................................................................................................................101
9.7.1
Inter Module Crossbar Switch (XBAR).........................................................................................................101
9.7.2
Module to module interconnects....................................................................................................................103
9.8
Memory map and register definition.............................................................................................................................104
9.8.1
System Reset Status Register (SIM_SRS)..................................................................................................... 105
9.8.2
System Background Debug Force Reset Register (SIM_SBDFR)................................................................ 107
9.8.3
System Device Identification Register: High (SIM_SDIDH)........................................................................107
9.8.4
System Device Identification Register: Low (SIM_SDIDL).........................................................................108
6
Title
Chapter 9
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Page
NXP Semiconductors
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