NXP Semiconductors MC68HC16Z1 User Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Microcontrollers
  5. MC68HC16Z1
  6. User manual

NXP Semiconductors MC68HC16Z1 User Manual

M68hc16z series
Hide thumbs
1
2
Table Of Contents
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
Table of Contents

Advertisement

Quick Links

Download this manual
Freescale Semiconductor
HC16
HC16
HC16
M68HC16Z Series
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Order this document by
MC68HC16ZUM/AD
MC68HC16Z1
MC68CK16Z1
MC68CM16Z1
MC68HC16Z2
MC68HC16Z3
MC68HC16Z4
MC68CK16Z4
User's Manual

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MC68HC16Z1 and is the answer not in the manual?

Questions and answers

Eswar
April 3, 2025

IS there any JTAG port? if not how to debug the device for MC68HC16Z1 mcus

0
1 comments:
Mr. Anderson
April 3, 2025

The NXP Semiconductors MC68HC16Z1 does not mention a JTAG port in the provided information. The available debugging methods include:

- Integrated assembly/editing/evaluation/programming environment
- Up to seven software breakpoints
- Re-usable in-circuit debugger (ICD) hardware
- RS-232C terminal I/O ports for serial communication evaluation
- Logic analyzer pod connectors
- Port Replacement Unit (PRU) to rebuild I/O ports used by address/data/control lines

These features support debugging and evaluation without a JTAG interface.

This answer is automatically generated

0

Subscribe to Our Youtube Channel

Related Manuals for NXP Semiconductors MC68HC16Z1

Summary of Contents for NXP Semiconductors MC68HC16Z1

  • Page 1 Freescale Semiconductor Order this document by MC68HC16ZUM/AD HC16 HC16 HC16 M68HC16Z Series MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 User’s Manual © Freescale Semiconductor, Inc., 2004. All rights reserved.
  • Page 2 Freescale Semiconductor, Inc. User’s Manual How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7...

  • Page 3: Table Of Contents

    Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title Page SECTION 1 INTRODUCTION SECTION 2 NOMENCLATURE Symbols and Operators ................2-1 CPU16 Register Mnemonics ..............2-2 Register Mnemonics ..................2-3 Conventions ....................2-6 SECTION 3 OVERVIEW M68HC16 Z-Series MCU Features ............3-1 3.1.1 Central Processor Unit (CPU16/CPU16L) .........3-1 3.1.2 System Integration Module (SIM/SIML) ..........3-1 3.1.3...
  • Page 4 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 4.2.7 Multiply and Accumulate Registers ...........4-5 Memory Management ................4-5 4.3.1 Address Extension ................4-6 4.3.2 Extension Fields ................4-6 Data Types ....................4-6 Memory Organization ................4-7 Addressing Modes ..................4-8 4.6.1 Immediate Addressing Modes ............4-9 4.6.2 Extended Addressing Modes ............4-10 4.6.3...
  • Page 5 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 4.14.4 Background Debug Mode ..............4-42 4.14.4.1 Enabling BDM .................4-42 4.14.4.2 BDM Sources ................4-42 4.14.4.3 Entering BDM ................4-42 4.14.4.4 BDM Commands ..............4-43 4.14.4.5 Returning from BDM ...............4-43 4.14.4.6 BDM Serial Interface ...............4-44 4.15 Recommended BDM Connection ............4-45 4.16...
  • Page 6 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 5.5.1.7 Function Codes ...............5-32 5.5.1.8 Data Size Acknowledge Signals ..........5-32 5.5.1.9 Bus Error Signal ..............5-33 5.5.1.10 Halt Signal ................5-33 5.5.1.11 Autovector Signal ..............5-33 5.5.2 Dynamic Bus Sizing ................5-33 5.5.3 Operand Alignment .................5-35 5.5.4 Misaligned Operands ..............5-35 5.5.5...
  • Page 7 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 5.8.1 Interrupt Exception Processing ............5-58 5.8.2 Interrupt Priority and Recognition ............5-58 5.8.3 Interrupt Acknowledge and Arbitration ..........5-59 5.8.4 Interrupt Processing Summary ............5-60 5.8.5 Interrupt Acknowledge Bus Cycles ..........5-61 Chip-Selects ....................5-61 5.9.1 Chip-Select Registers ..............5-63 5.9.1.1...
  • Page 8 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page SECTION 8 ANALOG-TO-DIGITAL CONVERTER General ......................8-1 External Connections ................8-1 8.2.1 Analog Input Pins ................8-2 8.2.2 Analog Reference Pins ..............8-3 8.2.3 Analog Supply Pins ................8-3 Programmer’s Model .................8-3 ADC Bus Interface Unit ................8-3 Special Operating Modes ................8-3 8.5.1 Low-Power Stop Mode ..............8-3...
  • Page 9 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page SECTION 9 QUEUED SERIAL MODULE General ......................9-1 QSM Registers and Address Map .............9-2 9.2.1 QSM Global Registers ...............9-2 9.2.1.1 Low-Power Stop Mode Operation ..........9-2 9.2.1.2 Freeze Operation ..............9-3 9.2.1.3 QSM Interrupts ................9-3 9.2.2 QSM Pin Control Registers ...............9-4 Queued Serial Peripheral Interface ............9-5...
  • Page 10 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE 10.1 General ....................10-1 10.2 MCCI Registers and Address Map ............10-2 10.2.1 MCCI Global Registers ..............10-2 10.2.1.1 Low-Power Stop Mode ............10-2 10.2.1.2 Privilege Levels ...............10-3 10.2.1.3 MCCI Interrupts ...............10-3 10.2.2 Pin Control and General-Purpose I/O ..........10-4...
  • Page 11 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 10.4.5.7 Idle-Line Detection ..............10-21 10.4.5.8 Receiver Wake-Up ..............10-22 10.4.5.9 Internal Loop .................10-22 10.5 MCCI Initialization .................10-23 SECTION 11 GENERAL-PURPOSE TIMER 11.1 General ....................11-1 11.2 GPT Registers and Address Map ............11-2 11.3 Special Modes of Operation ..............11-3 11.3.1...
  • Page 12 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION Obtaining Updated M68HC16 Z-Series MCU Mechanical Information ..B-8 Ordering Information ................B-8 APPENDIX C DEVELOPMENT SUPPORT M68MMDS1632 Modular Development System ........C-1 M68MEVB1632 Modular Evaluation Board ..........
  • Page 13 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page D.2.22 Master Shift Registers ..............D-22 D.2.23 Test Module Shift Count Register ..........D-22 D.2.24 Test Module Repetition Count Register ......... D-22 D.2.25 Test Module Control Register ............D-22 D.2.26 Test Module Distributed Register ...........
  • Page 14 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page D.7.1 MCCI Module Configuration Register ..........D-54 D.7.2 MCCI Test Register ................ D-55 D.7.3 SCI Interrupt Level Register/MCCI Interrupt Vector Register ..D-55 D.7.4 MCCI Interrupt Vector Register ............D-56 D.7.5 SPI Interrupt Level Register ............
  • Page 15 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page E.1.5 INITRAM.ASM ................E-11 E.1.6 INITSCI.ASM .................. E-12 Programming Examples ................. E-12 E.2.1 SIM Programming Examples ............E-13 E.2.1.1 Example 1 - Using Ports E and F ........... E-13 E.2.1.2 Example 2 - Using Chip-Selects ..........
  • Page 16 Freescale Semiconductor, Inc. M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 17 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Title Page MC68HC16Z1/CK16Z1/CM16Z1 Block Diagram ........... 3-4 MC68HC16Z2/Z3 Block Diagram ..............3-5 MC68HC16Z4/CK16Z4 Block Diagram ............3-6 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package ..................3-7 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package ..................3-8 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package ......
  • Page 18 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Title Page 5-12 Word Read Cycle Flowchart ................. 5-38 5-13 Write Cycle Flowchart .................. 5-39 5-14 CPU Space Address Encoding ..............5-41 5-15 Breakpoint Operation Flowchart ..............5-42 5-16 LPSTOP Interrupt Mask Level ..............5-43 5-17 Bus Arbitration Flowchart for Single Request ..........
  • Page 19 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Title Page 10-6 SCI Receiver Block Diagram ..............10-15 11-1 GPT Block Diagram ..................11-2 11-2 Prescaler Block Diagram ................11-9 11-3 Capture/Compare Unit Block Diagram ............11-11 11-4 Input Capture Timing Example ..............11-13 11-5 Pulse Accumulator Block Diagram .............
  • Page 20 8-Bit ADC Conversion Accuracy ..............A-69 A-36 Low Voltage 10-Bit ADC Conversion Accuracy ..........A-70 A-37 10-Bit ADC Conversion Accuracy ..............A-71 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package ..................B-2 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package ......B-3 Case 831A-01 — 132-Pin Package Dimensions ..........B-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package ..................B-5...
  • Page 21 Freescale Semiconductor, Inc. LIST OF TABLES Table Title Page M68HC16 Z-Series MCUs................1-1 Z-Series MCU Reference Frequencies ............1-2 M68HC16 Z-Series Pin Characteristics............3-11 M68HC16 Z-Series Driver Types ..............3-12 M68HC16 Z-Series Power Connections ............3-13 M68HC16 Z-Series Signal Characteristics ............ 3-13 M68HC16 Z-Series Signal Function..............
  • Page 22 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Title Page 5-25 Chip-Select Base and Option Register Reset Values ........5-69 5-26 CSBOOT Base and Option Register Reset Values........5-70 SRAM Configuration..................6-1 SRAM Array Address Space Type ..............6-2 ROM Array Space Field .................. 7-2 Wait States Field .....................
  • Page 23 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Title Page Typical Ratings, 5V, 16.78-MHz Operation .............A-3 Typical Ratings, 20.97-MHz Operation ............A-3 Typical Ratings, 25.17-MHz ................A-4 Thermal Characteristics ..................A-5 Low Voltage Clock Control Timing ..............A-6 16.78-MHz Clock Control Timing ..............A-7 20.97-MHz Clock Control Timing ..............A-8 A-10 25.17-MHz Clock Control Timing ..............A-9 A-11...
  • Page 24 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Title Page Show Cycle Enable Bits ..................D-6 Port E Pin Assignments.................D-10 Port F Pin Assignments.................D-11 Software Watchdog Divide Ratio..............D-12 Bus Monitor Time-Out Period................D-13 Pin Assignment Field Encoding..............D-16 CSPAR0 Pin Assignments ................D-16 D-10 CSPAR1 Pin Assignments ................D-17 D-11 Reset Pin Function of CS[10:6] ..............D-17...
  • Page 25 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Title Page D-44 PAMOD and PEDGE Effects.................D-71 D-45 PACLK[1:0] Effects..................D-71 D-46 OM/OL[5:2] Effects..................D-72 D-47 EDGE[4:1] Effects ..................D-72 D-48 CPR[2:0]/Prescaler Select Field..............D-73 D-49 PPR[2:0] Field ....................D-75 D-50 PWM Frequency Ranges ................D-76 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 26 Freescale Semiconductor, Inc. M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 27 Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION M68HC16 Z-series microcontrollers (including the MC68HC16Z1, MC68CM16Z1, MC68CK16Z1, MC68HC16Z2, MC68HC16Z3, MC68HC16Z4, and MC68CK16Z4) are high-speed 16-bit control units that are upwardly code compatible with M68HC11 controllers. All are members of the M68HC16 Family of modular microcontrollers.
  • Page 28 Freescale Semiconductor, Inc. Table 1-2 Z-Series MCU Reference Frequencies Nominal Reference Frequency Slow Fast (32.768 kHz) (4.194 MHz) MC68HC16Z1 — — MC68CM16Z1 MC68CK16Z1 — MC68HC16Z2 — MC68HC16Z3 — MC68HC16Z4 — MC68CK16Z4 — NOTES: 1. The nominal slow reference frequency is 32.768 kHz, but can range from 20 to 50 kHz.

  • Page 29: Nomenclature

    Freescale Semiconductor, Inc. SECTION 2 NOMENCLATURE The following tables show the nomenclature used throughout the M68HC16 Z-series manual. 2.1 Symbols and Operators Symbol Function Addition Subtraction (two’s complement) or negation Multiplication Division > Greater < Less Equal ≥ Equal or greater ≤...

  • Page 30: Cpu16 Register Mnemonics

    Freescale Semiconductor, Inc. 2.2 CPU16 Register Mnemonics Mnemonic Register Accumulator A Accumulator M Accumulator B Condition code register Accumulator D Accumulator E Extended addressing extension field MAC multiplier register MAC multiplicand register Index register X Index register Y Index register Z Address extension register Program counter Program counter extension field...

  • Page 31: Register Mnemonics

    Freescale Semiconductor, Inc. 2.3 Register Mnemonics Mnemonic Register ADCMCR ADC Module Configuration Register ADCTEST ADC Test Register ADCTL[0:1] ADC Control Registers [0:1] ADCSTAT ADC Status Register CFORC GPT Compare Force Register CREG SIM Test Module Control Register CR[0:F] QSM Command RAM [0:F] CSBARBT SIM Chip-Select Base Address Register Boot CSBAR[0:10]...
  • Page 32 Freescale Semiconductor, Inc. Mnemonic Register PICR SIM Periodic Interrupt Control Register PITR SIM Periodic Interrupt Timer Register PORTADA ADC Port ADA Data Register PORTC SIM Port C Data Register PORTE SIM Port E Data Register [0:1] PORTF SIM Port F Data Register [0:1] PORTGP GPT Port GP Data Register PORTMC...
  • Page 33 Freescale Semiconductor, Inc. Mnemonic Register SCSR QSM SCI Status Register SCSR[A:B] MCCI SCIA/B Status Registers [A:B] SIGHI ROM Signature Register High SIGLO ROM Signature Register Low SIMCR SIM Module Configuration Register SIMTR SIM Test Register SIMTRE SIM Test Register E SPCR MCCI SPI Control Register SPCR[0:3]...

  • Page 34: Conventions

    Freescale Semiconductor, Inc. 2.4 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a bit or bits. Clear refers specifically to establishing logic level zero on a bit or bits.

  • Page 35: Overview

    • Phase-locked loop (PLL) clock system • Expanded LPSTOP operation on SIML (MC68HC16Z4, MC68CK16Z4 only) 3.1.3 Standby RAM (SRAM) • 1-Kbyte static RAM (MC68HC16Z1/Z4 only) • 2-Kbyte static RAM (MC68HC16Z2 only) • 4-Kbyte static RAM (MC68HC16Z3 only) • External standby voltage supply input...

  • Page 36: Masked Rom Module (Mrm) - (Mc68Hc16Z2/Z3 Only)

    MCUs use only 20 address lines. ADDR[23:20] follow the state of ADDR19. 3.3 System Block Diagram and Pin Assignment Diagrams Figure 3-1 is a functional diagram of the MC68HC16Z1/CKZ1/CMZ1 MCU. Refer to Figure 3-2 for a functional diagram of the MC68HC16Z2/Z3 MCU.
  • Page 37 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 132-pin plastic surface-mount package. Figure 3-5 shows an MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 144-pin plastic surface-mount package. Figure 3-6 shows an MC68HC16Z4/CKZ4 pin assignment drawing based on a 132-pin plastic surface-mount package.
  • Page 38 MODCLK/PF0 CLKOUT CLOCK XTAL EXTAL BKPT IPIPE0 DDSYN BKPT/DSCLK IPIPE1 IPIPE1/DSI IPIPE0/DSO TEST QUOT FREEZE/QUOT DSCLK STBY FREEZE HC16Z1/CKZ1/CMZ1 BLOCK Figure 3-1 MC68HC16Z1/CK16Z1/CM16Z1 Block Diagram OVERVIEW M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 39 Freescale Semiconductor, Inc. PWMA CSBOOT PWMB PCLK ADDR23/CS10/ECLK IC4/OC5/OC1/PGP7 IC4/OC5/OC1 ADDR22/CS9/PC6 CHIP OC4/OC1/PGP6 OC4/OC1 CS[10:0] ADDR21/CS8/PC5 SELECT OC3/OC1/PGP5 OC3/OC1 ECLK ADDR20/CS7/PC4 OC2/OC1/PGP4 OC2/OC1 BGACK ADDR19/CS6/PC3 OC1/PGP3 FC2/CS5/PC2 IC3/PGP2 FC1/CS4/PC1 IC2/PGP1 FC0/CS3/PC0 IC1/PGP0 BGACK/CS2 BG/CS1 ADDR[23:19] BR/CS0 TXD/PQS7 PCS3/PQS6 PCS3 ADDR[18:0] PCS2/PQS5 PCS2 PCS1/PQS4...
  • Page 40 Freescale Semiconductor, Inc. PWMA CSBOOT PWMB PCLK ADDR23/CS10/ECLK IC4/OC5/OC1/PGP7 IC4/OC5/OC1 ADDR22/CS9/PC6 CHIP OC4/OC1/PGP6 OC4/OC1 CS[10:0] ADDR21/CS8/PC5 SELECT OC3/OC1/PGP5 OC3/OC1 ECLK ADDR20/CS7/PC4 OC2/OC1/PGP4 OC2/OC1 BGACK ADDR19/CS6/PC3 OC1/PGP3 FC2/CS5/PC2 IC3/PGP2 FC1/CS4/PC1 IC2/PGP1 FC0/CS3/PC0 IC1/PGP0 SIML BGACK/CS2 BG/CS1 ADDR[23:19] BR/CS0 TXDA/PMC7 TXDA RXDA/PMC6 RXDA TXDB/PMC5 TXDB...
  • Page 41 AS/PE5 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK HC16Z1/CKZ1/CMZ1/Z2/Z3 132-PIN QFP Figure 3-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package M68HC16 Z SERIES OVERVIEW USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 42 TXD/PQS7 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK HC16Z1/CKZ1/CMZ1/Z2/Z3 144-PIN QFP Figure 3-5 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package OVERVIEW M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 43 Freescale Semiconductor, Inc. TXDA/PMC7 BR/CS0 ADDR1 FC2/CS5/PC2 ADDR2 FC1/CS4/PC1 ADDR3 FC0/CS3/PC0 ADDR4 CSBOOT ADDR5 DATA0 ADDR6 DATA1 ADDR7 DATA2 ADDR8 DATA3 ADDR9 DATA4 ADDR10 DATA5 ADDR11 DATA6 MC68HC16Z4 ADDR12 DATA7 MC68CK16Z4 ADDR13 DATA8 MMMMM ADDR14 DATA9 ATWLYYWW ADDR15 ADDR16 ADDR17 DATA10 ADDR18 DATA11...
  • Page 44 Freescale Semiconductor, Inc. VRHP AS/PE5 AN5/PADA5 DS/PE4 AN4/PADA4 AVEC/PE2 AN3/PADA3 DSACK1/PE1 AN2/PADA2 DSACK0/PE0 AN1/PADA1 AN0/PADA0 ADDR0 VSSA DATA15 VDDA DATA14 DATA13 DATA12 DATA11 ADDR18 DATA10 ADDR17 ADDR16 ADDR15 MC68HC16Z4 DATA9 ADDR14 MC68CK16Z4 DATA8 ADDR13 MMMMM DATA7 ADDR12 DATA6 ATWLYYWW ADDR11 DATA5 ADDR10 DATA4...

  • Page 45: Pin Descriptions

    Freescale Semiconductor, Inc. 3.4 Pin Descriptions The following tables are a summary of the functional characteristics of M68HC16 Z- series MCU pins. Table 3-1 shows all inputs and outputs. Digital inputs and outputs use CMOS logic levels. An entry in the “Discrete I/O” column indicates that a pin can also be used for general-purpose input, output, or both.
  • Page 46 Freescale Semiconductor, Inc. Table 3-1 M68HC16 Z-Series Pin Characteristics (Continued) Output Input Input Discrete Port Mnemonic Driver Synchronized Hysteresis Designation — — PCLK PCS0/SS PQS3 PCS[3:1] PQS[6:4] — — — PWMA, PWMB — — RESET — — — — — —...

  • Page 47: Signal Descriptions

    Freescale Semiconductor, Inc. Table 3-3 M68HC16 Z-Series Power Connections Pin Mnemonic Description Standby RAM power STBY Clock synthesizer power DDSYN A/D converter power A/D reference voltage Microcontroller power 3.5 Signal Descriptions The following tables define the M68HC16 Z-series MCU signals. Table 3-4 shows sig- nal origin, type, and active state.
  • Page 48 Freescale Semiconductor, Inc. Table 3-4 M68HC16 Z-Series Signal Characteristics (Continued) Signal Signal Active Name Module Type State MISO Input/Output — MCCI Input/Output — MISO MODCLK Input — MOSI Input/Output — MCCI Input/Output — MOSI OC[5:1] Output — PADA[7:0] Input — Input —...
  • Page 49 Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function Mnemonic Signal Name Function ADDR[19:0] Address Bus 20-bit address bus used by CPU16 AN[7:0] ADC Analog Input Inputs to ADC multiplexer Address Strobe Indicates that a valid address is on the address bus AVEC Autovector Requests an automatic vector during interrupt acknowledge...

  • Page 50: Internal Register Map

    Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function (Continued) Mnemonic Signal Name Function PF[7:0] Port F Port F digital I/O port signals PGP[7:0] Port GP GPT digital I/O port signals PQS[7:0] Port QS QSM digital I/O port signals PWMA, PWMB Pulse Width Modulation Output for PWM QUOT...
  • Page 51 SRAM CONTROL 1K SRAM ARRAY (MAPPED TO 1K BOUNDARY) 8 BYTES $YFFB07 $YFFC00 512 BYTES $YFFDFF $FFFFFF HC16Z1/CKZ1/CMZ1 ADDRESS MAP Figure 3-8 MC68HC16Z1/CKZ1/CMZ1 Address Map M68HC16 Z SERIES OVERVIEW USER’S MANUAL 3-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 52 Freescale Semiconductor, Inc. $000000 $YFF700 64 BYTES $YFF73F $YFF820 ROM CONTROL 32 BYTES $YFF83F 8K ROM ARRAY $YFF900 (MAPPED TO 8K BOUNDARY) 64 BYTES $YFF93F $YFFA00 128 BYTES 2K SRAM ARRAY (MAPPED TO 2K BOUNDARY) $YFFA7F Z2 ONLY $YFFB00 SRAM CONTROL 8 BYTES $YFFB07 $YFFC00...

  • Page 53: Address Space Maps

    Freescale Semiconductor, Inc. 3.7 Address Space Maps Figures 3-11 through 3-16 show CPU16 address space for M68HC16 Z-series MCUs. Address space can be split into physically distinct program and data spaces by decod- ing the MCU function code outputs. Figures 3-11, 3-12, and 3-13 show the memory map of a system that has combined...
  • Page 54 IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. HC16Z1/CK/CM MEM MAP (C) Figure 3-11 MC68HC16Z1/CKZ1/CMZ1 Combined Program and Data Space Map OVERVIEW M68HC16 Z SERIES 3-20 USER’S MANUAL...
  • Page 55 Freescale Semiconductor, Inc. VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION $000000 $000000 BANK 0 0000 RESET — INITIAL ZK, SK, AND PK RESET AND EXCEPTION 0002 RESET — INITIAL PC VECTORS 0004 RESET — INITIAL SP 0006 RESET — INITIAL IZ (DIRECT PAGE) $010000 BANK 1 0008...
  • Page 56 Freescale Semiconductor, Inc. VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION $000000 $000000 BANK 0 0000 RESET — INITIAL ZK, SK, AND PK RESET AND EXCEPTION 0002 RESET — INITIAL PC VECTORS 0004 RESET — INITIAL SP 0006 RESET — INITIAL IZ (DIRECT PAGE) $010000 BANK 1 0008...
  • Page 57 IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. HC16Z1/CK/CM MEM MAP (S) Figure 3-14 MC68HC16Z1/CKZ1/CMZ1 Separate Program and Data Space Map M68HC16 Z SERIES OVERVIEW USER’S MANUAL...
  • Page 58 Freescale Semiconductor, Inc. VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION $000000 $000000 BANK 0 BANK 0 0000 RESET — INITIAL ZK, SK, AND PK $000008 0002 RESET — INITIAL PC EXCEPTION VECTORS $000008 0004 RESET — INITIAL SP $010000 $010000 0006 RESET —...
  • Page 59 Freescale Semiconductor, Inc. VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION $000000 $000000 BANK 0 BANK 0 0000 RESET — INITIAL ZK, SK, AND PK $000008 $000008 0002 RESET — INITIAL PC EXCEPTION VECTORS 0004 RESET — INITIAL SP $010000 $010000 0006 RESET —...
  • Page 60 Freescale Semiconductor, Inc. OVERVIEW M68HC16 Z SERIES 3-26 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 61: Central Processor Unit

    Freescale Semiconductor, Inc. SECTION 4 CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit (CPU16). For detailed infor- mation, refer to the CPU16 Reference Manual (CPU16RM/AD). 4.1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides addition- al capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and digital signal processing.
  • Page 62 Freescale Semiconductor, Inc. BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D (A:B) ACCUMULATOR E INDEX REGISTER X INDEX REGISTER Y INDEX REGISTER Z STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION FIELD SK MAC MULTIPLIER REGISTER HR MAC MULTIPLICAND REGISTER IR...

  • Page 63: Accumulators

    Freescale Semiconductor, Inc. 4.2.1 Accumulators The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In addition, accumulators A and B can be concatenated into a second 16-bit double ac- cumulator (D). Accumulators A, B, and D are general-purpose registers that hold operands and re- sults during mathematical and data manipulation operations.

  • Page 64: Condition Code Register

    Freescale Semiconductor, Inc. 4.2.5 Condition Code Register The 16-bit condition code register is composed of two functional blocks. The eight MSB, which correspond to the CCR on the M68HC11, contain the low-power stop con- trol bit and processor status flags. The eight LSB contain the interrupt priority field, the DSP saturation mode control bit, and the program counter address extension field.

  • Page 65: Address Extension Register And Address Extension Fields

    Freescale Semiconductor, Inc. SM — Saturate Mode Bit When SM is set and either EV or MV is set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit before overflow.

  • Page 66: Address Extension

    Freescale Semiconductor, Inc. 4.3.1 Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide. These resources include the index registers, program counter, and stack pointer. All address- ing modes use 20-bit addresses. Twenty-bit addresses are formed from a 16-bit byte address generated by an individ- ual CPU16 register and a 4-bit address extension contained in an associated exten- sion field.

  • Page 67: Memory Organization

    Freescale Semiconductor, Inc. Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, but use of the extension bits allows representation of numbers in the range –16 ($800000000) to 15.999969482 ($7FFFFFFFF).

  • Page 68: Addressing Modes

    Freescale Semiconductor, Inc. Address Type $0000 $0002 BYTE0 BYTE1 ± ± ± ± $0004 X OFFSET Y OFFSET X OFFSET Y OFFSET $0006 BCD1 BCD0 BCD1 BCD0 $0008 WORD 0 $000A WORD 1 $000C MSW LONG WORD 0 $000E LSW LONG WORD 0 $0010 MSW LONG WORD 1 $0012...

  • Page 69: Immediate Addressing Modes

    Freescale Semiconductor, Inc. Table 4-1 Addressing Modes Mode Mnemonic Description Index register X with accumulator E offset Accumulator Offset Index register Y with accumulator E offset Index register Z with accumulator E offset Extended Extended EXT20 20-bit extended IMM8 8-bit immediate Immediate IMM16 16-bit immediate...

  • Page 70: Extended Addressing Modes

    Freescale Semiconductor, Inc. 4.6.2 Extended Addressing Modes Regular extended mode instructions contain ADDR[15:0] in the word following the op- code. The effective address is formed by concatenating the EK field and the 16-bit byte address. EXT20 mode is used only by the JMP and JSR instructions. These instruc- tions contain a 20-bit effective address that is zero-extended to 24 bits to give the in- struction an even number of bytes.

  • Page 71: Use Of Cpu16 Indexed Mode To Replace M68Hc11 Direct Mode

    Freescale Semiconductor, Inc. 4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems, the direct addressing mode can be used to perform rapid ac- cesses to RAM or I/O mapped from $0000 to $00FF. The CPU16 uses the first 512 bytes of bank 0 for exception vectors.
  • Page 72 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (A ) + (B) ⇒ A ∆ ∆ ∆ ∆ ∆ Add B to A 370B — —...
  • Page 73 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (B) + (M) ⇒ B ∆ ∆ ∆ ∆ ∆ ADDB Add to B IND8, X —...
  • Page 74 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (B) • (M) ⇒ B ∆ ∆ ANDB AND B IND8, X — — — — —...
  • Page 75 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N ASRA Arithmetic Shift Right 370D — — — — — ASRB Arithmetic Shift Right 371D — —...
  • Page 76 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (B) • (M) ∆ ∆ BITB Bit Test B IND8, X — — — — — IND8, Y IND8, Z IMM8...
  • Page 77 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (PK : PC) - 2 ⇒ PK : PC Branch to Subroutine REL8 — — — —...
  • Page 78 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (D) − (M : M + 1) ∆ ∆ ∆ ∆ Compare D to Memory IND8, X —...
  • Page 79 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (E : D) / (IX) ∆ ∆ ∆ ∆ EDIVS Extended Signed 3729 — — — —...
  • Page 80 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N 〈ea〉 ⇒ PK : PC Jump EXT20 zb hh ll — — — — — — — — IND20, X zg gggg IND20, Y...
  • Page 81 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (M) ⇒ B ∆ ∆ ∆ LDAB Load B IND8, X — — — — IND8, Y IND8, Z IMM8 IND16, X...
  • Page 82 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N LPSTOP Low Power Stop If S 27F1 — 4, 20 — — — — — — — — then STOP else NOP ∆...
  • Page 83 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (M) ⇒ A ∆ ∆ ORAA OR A IND8, X — — — — — IND8, Y IND8, Z IMM8 IND16, X...
  • Page 84 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Pull Multiple Registers For mask bits 0 to 7: IMM8 4+2(N+1) PULM...
  • Page 85 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N ∆ ∆ ∆ ∆ RORW Rotate Right Word IND16, X 270E gggg — — — — IND16, Y 271E gggg...
  • Page 86 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (B) ⇒ M ∆ ∆ STAB Store B IND8, X — — — — — IND8, Y IND8, Z IND16, X 17CA...
  • Page 87 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (B) − (M) ⇒ B ∆ ∆ ∆ ∆ SUBB Subtract from B IND8, X — —...
  • Page 88 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N If (SM • (EV ∆ ∆ TMET Transfer Truncated MV)) 27B5 — — — — — —...
  • Page 89 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV EV N (D) ⇔ (IY) XGDY Exchange D with IY 37DC — — — — — — — — — (D) ⇔...
  • Page 90 Freescale Semiconductor, Inc. Table 4-3 Instruction Set Abbreviations and Symbols A — Accumulator A X — Register used in operation AM — Accumulator M M — Address of one memory byte M +1 — Address of byte at M + $0001 B —...

  • Page 91: Comparison Of Cpu16 And M68Hc11 Cpu Instruction Sets

    Freescale Semiconductor, Inc. 4.8 Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source-code compatible subset of the CPU16 instruction set. However, certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions, and some CPU16 instructions with the same mnemonics as M68HC11 CPU instructions operate differently.
  • Page 92 Freescale Semiconductor, Inc. Table 4-4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction CPU16 Implementation BCC only BCS only Generates a different stack frame Replaced by ANDP Replaced by ANDP Replaced by ANDP Replaced by AIS Replaced by AIX Replaced by AIY Replaced by AIS Replaced by AIX Replaced by AIY...

  • Page 93: Instruction Format

    Freescale Semiconductor, Inc. 4.9 Instruction Format CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte and followed by one or more operands. Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone. Page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0.

  • Page 94: Execution Model

    Freescale Semiconductor, Inc. 8-Bit Opcode with 8-Bit Operand Opcode Operand 8-Bit Opcode with 4-Bit Index Extensions Opcode X Extension Y Extension 8-Bit Opcode, Argument(s) Opcode Operand Operand(s) Operand(s) 8-Bit Opcode with 8-Bit Prebyte, No Argument Prebyte Opcode 8-Bit Opcode with 8-Bit Prebyte, Argument(s) Prebyte Opcode Operand(s)

  • Page 95: Microsequencer

    Freescale Semiconductor, Inc. IPIPE0 MICROSEQUENCER IPIPE1 INSTRUCTION PIPELINE DATA EXECUTION UNIT 16 EXEC UNIT MODEL Figure 4-5 Instruction Execution Model 4.10.1 Microsequencer The microsequencer controls the order in which instructions are fetched, advanced through the pipeline, and executed. It increments the program counter and generates multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that con- trol execution sequence.

  • Page 96: Execution Process

    Freescale Semiconductor, Inc. 4.11 Execution Process Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B. The execution unit can access operands in either stage A or stage B (stage B accesses are limited to 8-bit operands). When execution is complete, opcodes are moved from stage B to stage C, where they remain until the next instruc- tion is complete.

  • Page 97: Exceptions

    Freescale Semiconductor, Inc. Total execution time is calculated using the expression: Where: ) = Total clock periods per instruction ) = Clock periods used for internal operation ) = Clock periods used for program access ) = Clock periods used for operand access Refer to the CPU16 Reference Manual (CPU16RM/AD) for more information on this topic.

  • Page 98: Exception Stack Frame

    Freescale Semiconductor, Inc. Table 4-5 Exception Vector Table Vector Vector Address Type of Number Address Space Exception 0000 Reset — Initial ZK, SK, and PK 0002 Reset — Initial PC 0004 Reset — Initial SP 0006 Reset — Initial IZ (Direct Page) 0008 Breakpoint 000A...

  • Page 99: Exception Processing Sequence

    Freescale Semiconductor, Inc. 4.13.3 Exception Processing Sequence Exception processing is performed in four phases. Priority of all pending exceptions is evaluated and the highest priority exception is processed first. Processor state is stacked, then the CCR PK extension field is cleared. An exception vector number is acquired and converted to a vector address.

  • Page 100: Multiple Exceptions

    Freescale Semiconductor, Inc. 4.13.5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous excep- tions. Exception processing for multiple exceptions is completed by priority, from high- est to lowest.

  • Page 101: Ipipe0/Ipipe1 Multiplexing

    Freescale Semiconductor, Inc. 4.14.1.1 IPIPE0/IPIPE1 Multiplexing Six types of information are required to track pipeline activity. To generate the six state signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1. The multiplexed signals have two phases. State signals are active low. Table 4-6 shows the encoding scheme.

  • Page 102: Opcode Tracking And Breakpoints

    Freescale Semiconductor, Inc. Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged. Operand breakpoints are always acknowledged. There is no break- point acknowledge bus cycle when BDM is entered. Refer to 5.6.4.1 Breakpoint Ac- knowledge Cycle for more information about breakpoints.

  • Page 103: Bdm Commands

    Freescale Semiconductor, Inc. of BKPT or execution of the BGND instruction. IPIPE0 and IPIPE1 change function be- fore an exception signal can be generated. The development system must use FREEZE assertion as an indication that BDM has been entered. When BDM is exited, FREEZE is negated before initiation of normal bus cycles.

  • Page 104: Bdm Serial Interface

    Freescale Semiconductor, Inc. 4.14.4.6 BDM Serial Interface The BDM serial interface uses a synchronous protocol similar to that of the Freescale serial peripheral interface (SPI). Figure 4-7 is a diagram of the serial logic required to use BDM with a development system. DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS...

  • Page 105: Recommended Bdm Connection

    Freescale Semiconductor, Inc. 4.15 Recommended BDM Connection In order to use BDM development tools when an MCU is installed in a system, Freescale recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU. Refer to Figure 4-8.
  • Page 106 Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4-46 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 107: System Integration Module

    Freescale Semiconductor, Inc. SECTION 5 SYSTEM INTEGRATION MODULE This section is an overview of the system integration module (SIM). Refer to the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM capabilities. Refer to D.2 System Integration Module for information concerning the SIM address map and register structure.

  • Page 108: System Configuration

    Freescale Semiconductor, Inc. SYSTEM CONFIGURATION XTAL CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK SYSTEM PROTECTION CHIP-SELECTS CHIP-SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST FREEZE/QUOT Z SERIES SIM BLOCK Figure 5-1 System Integration Module Block Diagram 5.2 System Configuration The SIM configuration register (SIMCR) governs several aspects of system operation. The following paragraphs describe those configuration options controlled by SIMCR.

  • Page 109: Interrupt Arbitration

    Freescale Semiconductor, Inc. 5.2.2 Interrupt Arbitration Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi- tration between interrupt requests of the same priority is performed by serial conten- tion between IARB field bit values. Contention will take place whenever an interrupt request is acknowledged, even when there is only a single request pending.

  • Page 110: System Clock

    Freescale Semiconductor, Inc. 5.3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in clock rate during operation.

  • Page 111: Clock Sources

    Freescale Semiconductor, Inc. 5.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines the system clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock signal from an external reference frequency. The clock synthesizer control reg- ister (SYNCR) determines operating frequency and mode of operation.

  • Page 112: Clock Synthesizer Operation

    Freescale Semiconductor, Inc. If a fast or slow reference frequency is provided to the PLL from a source other than a crystal, or an external system clock signal is applied through the EXTAL pin, the XTAL pin must be left floating. 5.3.2 Clock Synthesizer Operation is used to power the clock circuits when the system clock is synthesized from DDSYN...
  • Page 113 Freescale Semiconductor, Inc. 0.1 µF 0.1 µF 0.1 µF 0.1 µF 18 kΩ 1, 2 DDSYN 0.01 µF 0.01 µF 0.01 µF DDSYN NORMAL OPERATING ENVIRONMENT HIGH-STABILITY OPERATING ENVIRONMENT 1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION. 2.
  • Page 114 Freescale Semiconductor, Inc. When a fast reference is used, three W bits are located in the PLL feedback path, en- abling frequency multiplication by a factor from one to eight. Three Y bits and the X bit are located in the VCO clock output path to provide the ability to slow the system clock without disturbing the PLL.
  • Page 115 Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Shaded cells represent values that exceed 16.78 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 116 Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 117 Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Shaded cells represent values that exceed 20.97 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 118 Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 119 Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Shaded cells represent values that exceed 25.17 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 120 Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Prescalers Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) Slow...
  • Page 121 Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) 000000...
  • Page 122 Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) 100000...
  • Page 123 Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) 000000...
  • Page 124 Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 ×...
  • Page 125 Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 × Value) = Value) = Value) 000000...
  • Page 126 Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus Prescaler [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11 = 2 × Value) = 2 ×...

  • Page 127: External Bus Clock

    Figure 5-6 summarizes the effects of the STSIM and STEXT bits when MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3 MCUs enter normal low-power stop mode. Any clock in the off state is held low. If the synthesizer VCO is turned off during low-power stop mode, there is a PLL relock delay after the VCO is turned back on.
  • Page 128 Freescale Semiconductor, Inc. NOTE The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP USING EXTERNAL CLOCK? USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? SET STSIM = 1 SET STSIM = 0 simclk...
  • Page 129 Freescale Semiconductor, Inc. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP LEAVE IMBCLK ON IN LPSTOP? SET STOP BITS FOR MODULES THAT WILL NOT BE ACTIVE IN LPSTOP SET STCPU SET STCPU = 0 Hz imbclk imbclk IN LPSTOP IN LPSTOP USING EXTERNAL CLOCK?

  • Page 130: System Protection

    Freescale Semiconductor, Inc. 5.4 System Protection The system protection block preserves reset status, monitors internal activity, and pro- vides periodic interrupt generation. Figure 5-8 is a block diagram of the submodule. MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST BERR BUS MONITOR SPURIOUS INTERRUPT MONITOR...

  • Page 131: Halt Monitor

    Freescale Semiconductor, Inc. Table 5-8 Bus Monitor Period BMT[1:0] Bus Monitor Time-Out Period 64 system clocks 32 system clocks 16 system clocks 8 system clocks The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter- nal to external bus cycles.
  • Page 132 Freescale Semiconductor, Inc. Both writes must occur before time-out in the order listed. Any number of instructions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the software watchdog timing (SWT[1:0]) field in SYPCR. SWP determines system clock prescaling for the watchdog timer and determines that one of two options, either no prescaling or prescaling by a factor of 512, can be select- ed.

  • Page 133: Periodic Interrupt Timer

    Freescale Semiconductor, Inc. Table 5-10 Software Watchdog Divide Ratio SWT[1:0] Divide Ratio Figure 5-9 is a block diagram of the watchdog timer and the clock control for the pe- riodic interrupt timer. EXTAL XTAL FREEZE MODCLK CRYSTAL PRESCALER OSCILLATOR CLOCK SELECT CLOCK AND DISABLE SELECT...

  • Page 134: Interrupt Priority And Vectoring

    Freescale Semiconductor, Inc. The periodic interrupt timer modulus counter is clocked by one of two signals. When the PLL is enabled (MODCLK = 1 during reset), f is used with a slow reference os- cillator; f 128 is used with fast reference oscillator. When the PLL is disabled (MOD- CLK = 0 during reset), f is used.

  • Page 135: Low-Power Stop Operation

    Freescale Semiconductor, Inc. The PIRQL field is compared to the CPU16 interrupt priority mask to determine wheth- er the interrupt is recognized. Table 5-12 shows PIRQL[2:0] priority values. Because of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority.
  • Page 136 Freescale Semiconductor, Inc. 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ DSACK1 DSACK0 DTACK IACK IRQ7 ADDR[3:0] ADDR[17:0] RS[4:1] DATA[15:8] DATA[15:0] D[7:0] 10 kΩ CSBOOT ADDR[17:1] A[16:0] DATA[15:0] DQ[15:0] 10 kΩ 10 kΩ ADDR[15:1] A[14:0] DATA[15:8] DQ[7:0] 10 kΩ...

  • Page 137: Bus Control Signals

    Freescale Semiconductor, Inc. The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal ad- dress outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides dy- namic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long- word transfers.

  • Page 138: Read/Write Signal

    Freescale Semiconductor, Inc. 5.5.1.5 Read/Write Signal The read/write signal (R/W) determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa.

  • Page 139: Bus Error Signal

    Freescale Semiconductor, Inc. 5.5.1.9 Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing requirements. Refer to 5.6.5 Bus Exception Control Cycles for more information.
  • Page 140 Freescale Semiconductor, Inc. Table 5-15 Effect of DSACK Signals DSACK1 DSACK0 Result Insert wait states in current bus cycle Complete cycle — Data bus port size is eight bits Complete cycle — Data bus port size is sixteen bits Reserved If the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob- tain the other 16 bits.

  • Page 141: Operand Alignment

    Freescale Semiconductor, Inc. 5.5.3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combi- nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs.

  • Page 142: Bus Operation

    Freescale Semiconductor, Inc. Table 5-16 Operand Alignment Current DATA DATA Next Transfer Case SIZ1 SIZ0 ADDR0 DSACK1 DSACK0 Cycle [15:8] [7:0] Cycle Byte to 8-bit port (even) — (OP0) Byte to 8-bit port (odd) (OP0) — Byte to 16-bit port (even) (OP0) —...

  • Page 143: Read Cycle

    Freescale Semiconductor, Inc. Descriptions are made in terms of individual system clock states, labelled {S0, S1, S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and does not correspond to any implemented machine state. A clock cycle consists of two successive states.
  • Page 144 Freescale Semiconductor, Inc. PERIPHERAL ADDRESS DEVICE (S0) 1) SET R/W TO READ 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS AND DS (S1) PRESENT DATA (S2) 1) DECODE ADDR, R/W, SIZ[1:0], DS 2) PLACE DATA ON DATA[15:0] OR DECODE DSACK (S3) DATA[15:8] IF 8-BIT DATA...
  • Page 145 Freescale Semiconductor, Inc. PERIPHERAL ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ACCEPT DATA (S2 + S3) ASSERT DS AND WAIT FOR DSACK (S3) 1) DECODE ADDRESS 2) LATCH DATA FROM DATA BUS...

  • Page 146: Cpu Space Cycles

    Freescale Semiconductor, Inc. Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle).

  • Page 147: Breakpoint Acknowledge Cycle

    Freescale Semiconductor, Inc. CPU SPACE CYCLES ADDRESS BUS FUNCTION CODE BREAKPOINT 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# ACKNOWLEDGE LOW POWER 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 STOP BROADCAST INTERRUPT...

  • Page 148: Lpstop Broadcast Cycle

    Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW CPU16 PERIPHERAL ACKNOWLEDGE BREAKPOINT 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE ALL ONES ON ADDR[4:2] 5) SET ADDR1 TO ONE 6) SET SIZE TO WORD 7) ASSERT AS AND DS ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING...

  • Page 149: Bus Exception Control Cycles

    Freescale Semiconductor, Inc. IP MASK LPSTOP MASK LEVEL Figure 5-16 LPSTOP Interrupt Mask Level 5.6.5 Bus Exception Control Cycles An external device or a chip-select circuit must assert at least one of the DSACK[1:0] signals or the AVEC signal to terminate a bus cycle normally. Bus exception control cycles are used when bus cycles are not terminated in the expected manner.

  • Page 150: Bus Errors

    Freescale Semiconductor, Inc. Table 5-17 DSACK, BERR, and HALT Assertion Results Type of Control Asserted on Rising Description Termination Signal Edge of State of Result S + 2 NORMAL DSACK Normal cycle terminate and continue. BERR HALT HALT DSACK Normal cycle terminate and halt. BERR Continue when HALT is negated.

  • Page 151: Double Bus Faults

    Freescale Semiconductor, Inc. NOTE The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an in- struction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the CPU16 instruction register, with indeterminate re- sults.

  • Page 152: External Bus Arbitration

    Freescale Semiconductor, Inc. The halt operation has no effect on bus arbitration. However, when external bus arbi- tration occurs while the MCU is halted, address and control signals go into a high-im- pedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states.

  • Page 153: Show Cycles

    Freescale Semiconductor, Inc. REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BUS REQUEST (BR) GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER TERMINATE ARBITRATION...

  • Page 154: Reset

    Freescale Semiconductor, Inc. 5.7 Reset Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. The RESET input is synchronized to the system clock. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted.

  • Page 155: Reset Mode Selection

    Freescale Semiconductor, Inc. Table 5-18 Reset Source Summary Reset Lines Asserted by Type Source Timing Cause Controller External External Synch RESET pin MSTRST CLKRST EXTRST Power up Asynch MSTRST CLKRST EXTRST Software watchdog Monitor Asynch Time out MSTRST CLKRST EXTRST Internal HALT assertion HALT Monitor...

  • Page 156: Data Bus Mode Selection

    Freescale Semiconductor, Inc. 5.7.3.1 Data Bus Mode Selection All data lines have weak internal pull-up devices. When pins are held high by the in- ternal pull-ups, the MCU uses a default operating configuration. However, specific lines can be held low externally during reset to achieve an alternate configuration. NOTE External bus loading can overcome the weak internal pull-up drivers on data bus lines and hold pins low during reset.
  • Page 157 Freescale Semiconductor, Inc. The mode configuration drivers are conditioned with R/W and DS to prevent conflicts between external devices and the MCU when reset is asserted. If external RESET is asserted during an external write cycle, R/W conditioning (as shown in Figure 5-18) prevents corruption of the data during the write.

  • Page 158: Clock Mode Selection

    Freescale Semiconductor, Inc. DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If DATA8 is held low during reset, these pins are assigned to I/O port E. DATA9 determines the function of interrupt request pins IRQ[7:1] and the clock mode select pin (MODCLK).

  • Page 159: Pin State During Reset

    Freescale Semiconductor, Inc. Table 5-20 Module Pin Functions Module Pin Mnemonic Function PADA[7:0]/AN[7:0] Discrete input Reference voltage Reference voltage DSI/IPIPE1 DSI/IPIPE1 DSO/IPIPE0 DSO/IPIPE0 BKPT/DSCLK BKPT/DSCLK PGP7/IC4/OC5 Discrete input PGP[6:3]/OC[4:1] Discrete input PGP[2:0]/IC[3:1] Discrete input Discrete input PCLK Discrete input PWMA, PWMB Discrete output PQS7/TXD Discrete input...

  • Page 160: Reset States Of Sim Pins

    Freescale Semiconductor, Inc. NOTE Pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. This de- creases additional I caused by digital inputs floating near mid-sup- ply level. 5.7.5.1 Reset States of SIM Pins Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance state or are driven to their inactive states.

  • Page 161: Reset Timing

    Freescale Semiconductor, Inc. 5.7.6 Reset Timing The RESET input must be asserted for a specified minimum period for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset.

  • Page 162: Use Of The Three-State Control Pin

    Freescale Semiconductor, Inc. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and MSTRST is asserted for at least four clock cycles, these modules reset. V ramp time and VCO frequency ramp time determine how long the four cy- cles take.

  • Page 163: Reset Processing Summary

    Freescale Semiconductor, Inc. NOTE When TSC assertion takes effect, internal signals are forced to val- ues that can cause inadvertent mode selection. Once the output driv- ers change state, the MCU must be powered down and restarted before normal operation can resume. 5.7.9 Reset Processing Summary To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary.
  • Page 164 Freescale Semiconductor, Inc. 5.8 Interrupts Interrupt recognition and servicing involve complex interaction between the SIM, the CPU16, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process. Chip-select logic can also be used to re- spond to interrupt requests.

  • Page 165: Interrupt Acknowledge And Arbitration

    Freescale Semiconductor, Inc. Interrupt requests are sampled on consecutive falling edges of the system clock. In- terrupt request input circuitry has hysteresis. To be valid, a request signal must be as- serted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending.

  • Page 166: Interrupt Processing Summary

    Freescale Semiconductor, Inc. Although arbitration is intended to deal with simultaneous requests of the same inter- rupt level, it always takes place, even when a single source is requesting service. This is important for two reasons: the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early by a bus error.

  • Page 167: Interrupt Acknowledge Bus Cycles

    Freescale Semiconductor, Inc. 3. Request priority is latched into the CCR IP field from the address bus. D. Modules or external peripherals that have requested interrupt service decode the priority value in ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration by IARB contention takes place.
  • Page 168 Freescale Semiconductor, Inc. 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ DSACK1 DSACK0 DTACK IACK IRQ7 ADDR[3:0] ADDR[17:0] RS[4:1] DATA[15:8] DATA[15:0] D[7:0] 10 kΩ CSBOOT ADDR[17:1] A[16:0] DATA[15:0] DQ[15:0] 10 kΩ 10 kΩ ADDR[15:1] A[14:0] DATA[15:8] DQ[7:0] 10 kΩ...

  • Page 169: Chip-Select Registers

    Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all chip- selects.

  • Page 170: Chip-Select Pin Assignment Registers

    Freescale Semiconductor, Inc. Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR[10:0] and CSBARBT). However, because the logic state of ADDR20 is al- ways the same as the state of ADDR19 in the MCU, the largest usable block size is 512 Kbytes.

  • Page 171: Chip-Select Base Address Registers

    Freescale Semiconductor, Inc. Port size determines the way in which bus transfers to an external address are allo- cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. Port size and transfer size affect how the chip-select signal is asserted. Refer to 5.9.1.3 Chip-Select Option Registers for more information.

  • Page 172: Chip-Select Option Registers

    Freescale Semiconductor, Inc. The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size. Because the logic state of ADDR[23:20] follows that of ADDR19 in the CPU16, maxi- mum block size is 512 Kbytes, and addresses from $080000 to $F7FFFF are inacces- sible.

  • Page 173: Portc Data Register

    Freescale Semiconductor, Inc. SPACE[1:0] determines the address space in which a chip-select is asserted. An ac- cess must have the space type represented by the SPACE[1:0] encoding in order for a chip-select signal to be asserted. IPL[2:0] contains an interrupt priority mask that is used when chip-select logic is set to trigger on external interrupt acknowledge cycles.

  • Page 174: Using Chip-Select Signals For Interrupt Acknowledge

    Freescale Semiconductor, Inc. 5.9.3 Using Chip-Select Signals for Interrupt Acknowledge Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge bus cycles use CPU space access. Refer to 5.6.4 CPU Space Cycles 5.8 Inter- rupts for more information. There are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle.

  • Page 175: Chip-Select Reset Operation

    Freescale Semiconductor, Inc. 4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte when using an 8-bit port. If an interrupting device does not provide a vector number, an autovector acknowledge must be generated, either by asserting the AVEC pin or by generating AVEC internally using the chip-select option register.

  • Page 176: Parallel Input/Output Ports

    Freescale Semiconductor, Inc. However, the internal pull-up driver can be overcome by bus loading effects. To en- sure a particular configuration out of reset, use an active device to put DATA0 in a known state during reset. The base address field in the boot chip-select base address register CSBARBT has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the CSBOOT signal is asserted.

  • Page 177: Data Registers

    Freescale Semiconductor, Inc. 5.10.3 Data Registers A write to the port E and port F data registers (PORTE[0:1] and PORTF[0:1]) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of a data register returns the value at the pin only if the pin is configured as a discrete input.
  • Page 178 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5-72 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 179: Standby Ram Module

    M68CM16 Z-series version. Refer to Table 6-1 for appropriate SRAM array size. The SRAM is especially useful for system stacks and variable storage. Table 6-1 SRAM Configuration Z-Series Device Array Size MC68HC16Z1 1 Kbyte MC68CK16Z1 MC68CM16Z1 MC68HC16Z4 MC68CK16Z4 MC68HC16Z2...

  • Page 180: Sram Array Address Mapping

    Freescale Semiconductor, Inc. 6.2 SRAM Array Address Mapping Base address registers RAMBAH and RAMBAL are used to specify the SRAM array base address in the memory map. RAMBAH and RAMBAL can only be written while the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock (RAMMCR RLCK = 0) is disabled.

  • Page 181: Reset

    Freescale Semiconductor, Inc. (SRAM standby current) values may vary while V transitions occur. Refer to PENDIX A ELECTRICAL CHARACTERISTICS for standby switching and power con- sumption specifications. 6.6 Reset Reset places the SRAM in low-power stop mode, enables program space access, and clears the base address registers and the register lock bit.
  • Page 182 Freescale Semiconductor, Inc. STANDBY RAM MODULE M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 183: Masked Rom Module

    Freescale Semiconductor, Inc. SECTION 7 MASKED ROM MODULE The masked ROM module (MRM) is only available with the MC68HC16Z2 and the MC68HC16Z3. The MRM consists of a fixed-location control register block and an 8- Kbyte mask-programmed read-only memory array that can be mapped to any 8-Kbyte boundary in the system memory map.

  • Page 184: Mrm Array Address Space Type

    Freescale Semiconductor, Inc. The MRM array can be mapped to any 8-Kbyte boundary in the memory map, but must not overlap other module control registers (overlap makes the registers inaccessible). If the array overlaps the MRM register block, addresses in the register block are ac- cessed instead of the corresponding ROM array addresses.

  • Page 185: Low-Power Stop Mode Operation

    Freescale Semiconductor, Inc. Table 7-2 Wait States Field Number of WAIT[1:0] Clocks per Transfer Wait States –1 Refer to 5.6 Bus Operation for more information concerning access times. 7.5 Low-Power Stop Mode Operation Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in MRMCR places the MRM in low-power stop mode.
  • Page 186 Freescale Semiconductor, Inc. MASKED ROM MODULE M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 187: General

    Freescale Semiconductor, Inc. SECTION 8 ANALOG-TO-DIGITAL CONVERTER This section is an overview of the analog-to-digital converter module (ADC). Refer to the ADC Reference Manual (ADCRM/AD) for a comprehensive discussion of ADC ca- pabilities. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for ADC timing and electrical specifications.

  • Page 188: Analog Input Pins

    Freescale Semiconductor, Inc. V DDA V SSA SUPPLY V RH REFERENCE V RL RC DAC ARRAY AN7/PADA7 AN6/PADA6 COMPARATOR ANALOG AN5/PADA5 AN4/PADA4 AND SAMPLE AN3/PADA3 AN2/PADA2 BUFFER AMP AN1/PADA1 AN0/PADA0 RESERVED RESERVED MODE RESERVED RESERVED INTERNAL RESULT 0 V RH TIMING CONNECTIONS V RL...

  • Page 189: Analog Reference Pins

    Freescale Semiconductor, Inc. 8.2.2 Analog Reference Pins Separate high (V ) and low (V ) analog reference voltages are connected to the an- alog reference pins. The pins permit connection of regulated and filtered supplies that allow the ADC to achieve its highest degree of accuracy. 8.2.3 Analog Supply Pins Pins V and V...

  • Page 190: Freeze Mode

    Freescale Semiconductor, Inc. STOP is set during system reset, and must be cleared before the ADC can be used. Because analog circuit bias currents are turned off during low-power stop mode, the ADC requires recovery time after STOP is cleared. Execution of the CPU16 LPSTOP command places the entire modular microcontroller in low-power stop mode.

  • Page 191: Sample Capacitor And Buffer Amplifier

    Freescale Semiconductor, Inc. Table 8-2 Multiplexer Channel Sources [CD:CA] Value Input Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 1101 – V ) / 2 1110 1111 Test/Reserved 8.6.2 Sample Capacitor and Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier.

  • Page 192: Comparator

    Freescale Semiconductor, Inc. 8.6.4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower than the sampled input voltage. Comparator output is fed to the digital control logic, which sets or clears each bit in the successive approx- imation register in sequence, MSB first.

  • Page 193: Sample Time

    Freescale Semiconductor, Inc. Table 8-3 Prescaler Output Minimum Maximum PRS[4:0] ADC Clock System Clock System Clock %00000 Reserved — — %00001 System Clock/4 2.0 MHz 8.4 MHz %00010 System Clock/6 3.0 MHz 12.6 MHz %00011 System Clock/8 4.0 MHz 16.8 MHz …...

  • Page 194: Conversion Parameters

    Freescale Semiconductor, Inc. 8.7.5.1 Conversion Parameters Table 8-5 describes the conversion parameters controlled by bits in ADCTL1. Table 8-5 Conversion Parameters Controlled by ADCTL1 Conversion Parameter Description The value of the channel selection field (CD:CA) in ADCTL1 determines which multiplexer inputs are used in a conversion sequence. There are Conversion channel 16 possible inputs.
  • Page 195 Freescale Semiconductor, Inc. Mode 2 — A single conversion is performed on each of four sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is set as each register is filled.
  • Page 196 Freescale Semiconductor, Inc. Table 8-7 Single-Channel Conversions (MULT = 0) S8CM Input Result Register RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] RSLT[0:3] RSLT[0:3] ) / 2 RSLT[0:3] – Test/Reserved RSLT[0:3] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7]...
  • Page 197 Freescale Semiconductor, Inc. Table 8-8 Multiple-Channel Conversions (MULT = 1) S8CM Input Result Register RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 Reserved RSLT0 Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT0 RSLT1 ) / 2 RSLT2 – Test/Reserved RSLT3 RSLT0 RSLT1 RSLT2 RSLT3...

  • Page 198: Conversion Timing

    Freescale Semiconductor, Inc. 8.7.6 Conversion Timing Total conversion time is made up of initial sample time, transfer time, final sample time, and resolution time. Initial sample time is the time during which a selected input chan- nel is connected to the sample buffer amplifier through a sample capacitor. During transfer time, the sample capacitor is disconnected from the multiplexer, and the RC DAC array is driven by the sample buffer amp.

  • Page 199: Successive Approximation Register

    Freescale Semiconductor, Inc. TRANSFER CONVERSION TO RESULT REGISTER AND SET INITIAL FINAL SAMPLE TRANSFER SAMPLE TIME TIME TIME RESOLUTION TIME (2 ADC CLOCKS) 6 CYCLES CYCLES CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3...

  • Page 200: Pin Considerations

    Freescale Semiconductor, Inc. Table 8-9 Result Register Formats Result Data Format Description Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, Unsigned bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero right-justified format when read.
  • Page 201 Freescale Semiconductor, Inc. SAMPLE COMPARATOR RC DAC 8 CHANNELS TOTAL ARRAY REF 1 REF 2 NOTES: 1. TWO SAMPLE AMPS EXIST ON THE ADC WITH EIGHT CHANNELS ON EACH SAMPLE AMP. ADC 8CH SAMPLE AMP Figure 8-4 Analog Input Circuitry Since the sample amplifier is powered by V and V , it can accurately transfer...

  • Page 202: Analog Supply Filtering And Grounding

    Freescale Semiconductor, Inc. .010 .020 .030 5.100 5.110 5.120 5.130 INPUT IN VOLTS (V = 5.120 V, V = 0 V) ADC CLIPPING Figure 8-5 Errors Resulting from Clipping 8.8.3 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding.
  • Page 203 Freescale Semiconductor, Inc. Grounding is the most important factor influencing analog circuit performance in mixed signal systems (or in stand-alone analog systems). Close attention must be paid to avoid introducing additional sources of noise into the analog circuitry. Common sourc- es of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately.

  • Page 204: Accommodating Positive/Negative Stress Conditions

    Freescale Semiconductor, Inc. NOTE This star-point scheme still requires adequate grounding for digital and analog subsystems in addition to the star-point ground. Other suggestions for PCB layout in which the ADC is employed include the following: • The analog ground must be low impedance to all analog ground points in the cir- cuit.

  • Page 205: Analog Input Considerations

    Freescale Semiconductor, Inc. The current out of the pin (I ) under negative stress is determined by the following equation: – STRESS ------------------------------------------ - STRESS where: = Adjustable voltage source STRESS = Parasitic bipolar base/emitter voltage (refer to V NEGCLAMP APPENDIX A ELECTRICAL CHARACTERISTICS) = Source impedance (10K resistor in...
  • Page 206 Freescale Semiconductor, Inc. TYPICAL MUX CHIP FILTERING AND (MC54HC4051, MC74HC4051, ANALOG SIGNAL SOURCE INTERCONNECT INTERCONNECT MC54HC4052, MC74HC4052, MC54HC4053, ETC.) R SOURCE R FILTER 0.1 µF C SOURCE C FILTER C MUXIN R SOURCE R FILTER 0.1 µF C SOURCE C FILTER C MUXIN R SOURCE R FILTER...

  • Page 207: Analog Input Pins

    Freescale Semiconductor, Inc. 8.8.6 Analog Input Pins Analog inputs should have low AC impedance at the pins. Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part. Ideally, that capacitor should be as large as possible (within the practi- cal range of capacitors that still have good high frequency characteristics).

  • Page 208: Settling Time For The External Circuit

    Freescale Semiconductor, Inc. Figure 8-10, R and C comprise the user's external filter circuit. C is the internal sample capacitor. Each channel has its own capacitor. C is never precharged; it re- tains the value of the last sample. V is an internal voltage source used to precharge the DAC capacitor array (C ) before each sample.

  • Page 209: Error Resulting From Leakage

    Freescale Semiconductor, Inc. Table 8-10 External Circuit Settling Time (10-Bit Conversions) Source Resistance (R Filter Capacitor 100 Ω 1 kΩ 10 kΩ 100 kΩ 1 µF 760 µs 7.6 ms 76 ms 760 ms .1 µF 76 µs 760 µs 7.6 ms 76 ms .01 µF...
  • Page 210 Freescale Semiconductor, Inc. ANALOG-TO-DIGITAL CONVERTER M68HC16 Z SERIES 8-24 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 211: Queued Serial Module

    The QSM contains two serial interfaces: the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). Figure 9-1 is a block diagram of the QSM. The QSM is present on the MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3 microcontrollers. MISO/PQS0 MOSI/PQS1...

  • Page 212: Qsm Registers And Address Map

    Freescale Semiconductor, Inc. The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates in either full- or half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A modulus-type baud rate generator provides rates from 110 baud to 781 kbaud with a 25.17 MHz system clock.

  • Page 213: Freeze Operation

    Freescale Semiconductor, Inc. 9.2.1.2 Freeze Operation The freeze FRZ[1:0] bits in QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU16 enters background debug mode. At the present time, FRZ0 has no effect; setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE asser- tion.

  • Page 214: Qsm Pin Control Registers

    Freescale Semiconductor, Inc. 9.2.2 QSM Pin Control Registers The QSM uses nine pins. Eight of the pins can be used for serial communication or for parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.

  • Page 215: Queued Serial Peripheral Interface

    Freescale Semiconductor, Inc. 9.3 Queued Serial Peripheral Interface The queued serial peripheral interface (QSPI) is used to communicate with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI sys- tems found on other Freescale products, but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire transfers.

  • Page 216: Qspi Registers

    Freescale Semiconductor, Inc. The serial transfer length is programmable from eight to sixteen bits, inclusive. An in- ter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 system clocks). A dedicated 80-byte RAM is used to store received data, data to be transmitted, and a queue of commands.

  • Page 217: Status Register

    Freescale Semiconductor, Inc. 9.3.1.2 Status Register SPSR contains information concerning the current serial transmission. Only the QSPI can set the bits in this register. The CPU16 reads SPSR to obtain QSPI status infor- mation and writes SPSR to clear status flags. 9.3.2 QSPI RAM The QSPI contains an 80-byte block of dual-ported static RAM that can be accessed by both the QSPI and the CPU16.

  • Page 218: Command Ram

    Freescale Semiconductor, Inc. 9.3.2.3 Command RAM Command RAM is used by the QSPI in master mode. The CPU16 writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes.

  • Page 219: Qspi Operating Modes

    Freescale Semiconductor, Inc. The internal pointer is initialized to the same value as NEWQP. During normal opera- tion, the command pointed to by the internal pointer is executed, the value in the inter- nal pointer is copied into CPTQP, the internal pointer is incremented, and then the sequence repeats.
  • Page 220 Freescale Semiconductor, Inc. BEGIN INITIALIZE QSM GLOBAL REGISTERS INITIALIZE PQSPAR, PORTQS, AND DDRQS IN THIS ORDER QSPI INITIALIZATION INITIALIZE QSPI CONTROL REGISTERS INITIALIZE QSPI RAM ENABLE QSPI MSTR = 1 ? QSPI FLOW 1 Figure 9-4 Flowchart of QSPI Initialization Operation QUEUED SERIAL MODULE M68HC16 Z SERIES 9-10...
  • Page 221 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (MASTER MODE) IS QSPI DISABLED HAS NEWQP WORKING QUEUE POINTER BEEN WRITTEN CHANGED TO NEWQP READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL CHIP-SELECT(S) IS PCS TO SCK DELAY EXECUTE PROGRAMMED DELAY PROGRAMMED EXECUTE STANDARD DELAY...
  • Page 222 Freescale Semiconductor, Inc. WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE BIT ASSERTED NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY AFTER TRANSFER EXECUTE PROGRAMMED DELAY ASSERTED EXECUTE STANDARD DELAY QSPI MSTR2 FLOW 3 Figure 9-6 Flowchart of QSPI Master Operation (Part 2) QUEUED SERIAL MODULE M68HC16 Z SERIES 9-12...
  • Page 223 Freescale Semiconductor, Inc. IS THIS THE ASSERT SPIF LAST COMMAND STATUS FLAG IN THE QUEUE IS INTERRUPT ENABLE BIT REQUEST INTERRUPT SPIFIE ASSERTED INCREMENT WORKING IS WRAP RESET WORKING QUEUE QUEUE POINTER ENABLE BIT POINTER TO NEWQP OR $0000 ASSERTED DISABLE QSPI IS HALT HALT QSPI AND...
  • Page 224 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (SLAVE MODE) IS QSPI DISABLED HAS NEWQP QUEUE POINTER BEEN WRITTEN CHANGED TO NEWQP READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS...
  • Page 225 Freescale Semiconductor, Inc. IS THIS THE ASSERT SPIF LAST COMMAND STATUS FLAG IN THE QUEUE IS INTERRUPT ENABLE BIT REQUEST INTERRUPT SPIFIE ASSERTED INCREMENT WORKING IS WRAP RESET WORKING QUEUE QUEUE POINTER ENABLE BIT POINTER TO NEWQP OR $0000 ASSERTED DISABLE QSPI IS HALT HALT QSPI AND...

  • Page 226: Master Mode

    Freescale Semiconductor, Inc. Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0.
  • Page 227 Freescale Semiconductor, Inc. Data transfer is synchronized with the internally-generated serial clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing data from the MOSI pin and to latch incoming data from the MISO pin.
  • Page 228 Freescale Semiconductor, Inc. Table 9-3 Bits Per Transfer BITS[3:0] Bits Per Transfer 0000 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 1001 1010 1011 1100 1101 1110 1111 Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to com- plete conversion.

  • Page 229: Master Wrap-Around Mode

    Freescale Semiconductor, Inc. QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the QSPI executes the command at the command RAM address pointed to by NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted.

  • Page 230: Slave Mode

    Freescale Semiconductor, Inc. 9.3.5.3 Slave Mode Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus master. Slave mode is typically used on a multi-master SPI bus. Only one device can be bus master (operate in master mode) at any given time.

  • Page 231: Slave Wrap-Around Mode

    Freescale Semiconductor, Inc. The QSPI transmits as many bits as it receives at each queue address, until the BITS[3:0] value is reached or SS is negated. SS does not need to go high between transfers as the QSPI transfers data until reaching the end of the queue, whether SS remains low or is toggled between transfers.
  • Page 232 Freescale Semiconductor, Inc. (WRITE-ONLY) SCDR Tx BUFFER TRANSMITTER BAUD RATE CLOCK DDRQS (D7) 10 (11)-BIT Tx SHIFT REGISTER PIN BUFFER H (8) 7 6 5 4 3 2 1 0 L AND CONTROL PARITY GENERATOR TRANSMITTER CONTROL LOGIC SCSR STATUS REGISTER SCCR1 CONTROL REGISTER 1 TDRE INTERNAL...
  • Page 233 Freescale Semiconductor, Inc. RECEIVER BAUD RATE CLOCK 10 (11)-BIT Rx SHIFT REGISTER DATA PIN BUFFER (8) 7 6 5 4 3 2 1 0 RECOVERY ALL ONES PARITY DETECT WAKE-UP LOGIC SCCR1 CONTROL REGISTER 1 SCDR Rx BUFFER (READ-ONLY) SCSR STATUS REGISTER SCI Tx SCI INTERRUPT INTERNAL...

  • Page 234: Sci Registers

    Freescale Semiconductor, Inc. 9.4.1 SCI Registers The SCI programming model includes the QSM global and pin control registers, and four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one sta- tus register (SCSR), and one data register (SCDR). Refer to D.6 Queued Serial Mod- for register bit and field definitions.

  • Page 235: Sci Pins

    Freescale Semiconductor, Inc. 9.4.2 SCI Pins Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated with the SCI. TXD can be used by the SCI or for general-purpose I/O. TXD function is controlled by PQSPA7 in the port QS pin assignment register (PQSPAR) and TE in SCI control register 1 (SCCR1).

  • Page 236: Baud Clock

    Freescale Semiconductor, Inc. Table 9-4 Serial Frame Formats 10-Bit Frames Start Data Parity/Control Stop — — 11-Bit Frames Start Data Parity/Control Stop 9.4.3.3 Baud Clock The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI control register 0 (SCCR0).

  • Page 237: Transmitter Operation

    Freescale Semiconductor, Inc. Table 9-5 Effect of Parity Checking on Data Size Result 8 data bits 7 data bits, 1 parity bit 9 data bits 8 data bits, 1 parity bit 9.4.3.5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register (TDR) located in the SCI data register (SCDR).

  • Page 238: Receiver Operation

    Freescale Semiconductor, Inc. If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark). When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames are transmitted.

  • Page 239: Idle-Line Detection

    Freescale Semiconductor, Inc. RDRF must be cleared before the next transfer from the shifter can take place. If RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR) flag in SCSR is set. OR indicates that RDR needs to be serviced faster. When OR is set, the data in RDR is preserved, but the data in the serial shifter is lost.

  • Page 240: Internal Loop Mode

    Freescale Semiconductor, Inc. A receiver is placed in wake-up mode by setting the RWU bit in SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although the CPU16 can clear RWU, it is normally cleared by hardware during wake-up. The WAKE bit in SCCR1 determines which type of wake-up is used.

  • Page 241: M68Hc16 Z Series

    Freescale Semiconductor, Inc. SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE This section is an overview of the multichannel communication interface (MCCI) mod- ule. Refer to the MCCI Reference Manual (MCCIRM/AD) for more information on MCCI capabilities. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS MCCI timing and electrical specifications.

  • Page 242: Mcci Registers And Address Map

    Freescale Semiconductor, Inc. The SCI is a universal asynchronous receiver transmitter (UART) serial interface with a standard non-return to zero (NRZ) mark/space format. It operates in either full- or half-duplex mode. It also contains separate transmit and receive enable bits and a double-transmit buffer.

  • Page 243: Privilege Levels

    Freescale Semiconductor, Inc. To ensure that the MCCI stops in a known state, assert the STOP bit before executing the CPU LPSTOP instruction. Before asserting the STOP bit, disable the SPI (clear the SPE bit) and disable the SCI receivers and transmitters (clear the RE and TE bits). Complete transfers in progress before disabling the SPI and SCI interfaces.

  • Page 244: Pin Control And General-Purpose I/O

    Freescale Semiconductor, Inc. Select a value for INTV so that each MCCI interrupt vector corresponds to one of the user-defined vectors ($40–$FF). Refer to the CPU16 Reference Manual (CPU16RM/ AD) for additional information on interrupt vectors. 10.2.2 Pin Control and General-Purpose I/O The eight pins used by the SPI and SCI subsystems have alternate functions as gen- eral-purpose I/O pins.
  • Page 245 Freescale Semiconductor, Inc. INTERNAL MISO MCU CLOCK PMC0 MOSI MODULUS PMC1 COUNTER 8/16-BIT SHIFT REGISTER READ DATA BUFFER CLOCK SPI CLOCK (MASTER) SELECT CLOCK PMC2 LOGIC PMC3 SHIFT CONTROL LOGIC MSTR SPI CONTROL SPI STATUS REGISTER SPI CONTROL REGISTER SPI INTERRUPT INTERNAL REQUEST DATA BUS...

  • Page 246: Spi Registers

    Freescale Semiconductor, Inc. Error-detection logic is included to support interprocessor interfacing. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically dis- ables SPI output drivers if more than one MCU simultaneously attempts to become bus master.

  • Page 247: Spi Operating Modes

    Freescale Semiconductor, Inc. Table 10-3 SPI Pin Functions Pin Name Mode Function Master in, slave out (MISO) Master Provides serial data input to the SPI Slave Provides serial data output from the SPI Master out, slave in (MOSI) Master Provides serial output from the SPI Slave Provides serial input to the SPI Serial clock (SCK)

  • Page 248: Slave Mode

    Freescale Semiconductor, Inc. Data transfer is synchronized with the internally-generated serial clock (SCK). Control bits CPHA and CPOL in SPCR control clock phase and polarity. Combinations of CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing data from the MOSI pin and latches incoming data from the MISO pin.

  • Page 249: Cpha = 0 Transfer Format

    Freescale Semiconductor, Inc. 10.3.4.1 CPHA = 0 Transfer Format Figure 10-3 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA equals zero. Two waveforms are shown for SCK: one for CPOL equal to zero and an- other for CPOL equal to one.

  • Page 250: Cpha = 1 Transfer Format

    Freescale Semiconductor, Inc. 10.3.4.2 CPHA = 1 Transfer Format Figure 10-4 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA equals one. Two waveforms are shown for SCK, one for CPOL equal to zero and an- other for CPOL equal to one.

  • Page 251: Spi Serial Clock Baud Rate

    Freescale Semiconductor, Inc. 10.3.5 SPI Serial Clock Baud Rate Baud rate is selected by writing a value from two to 255 into SPBR[7:0] in the SPCR of the master MCU. Writing an SPBR[7:0] value into the SPCR of the slave device has no effect.

  • Page 252: Write Collision

    Freescale Semiconductor, Inc. 10.3.8 Write Collision A write collision occurs if an attempt is made to write the SPDR while a transfer is in progress. Since the SPDR is not double buffered in the transmit direction, a successful write to SPDR would cause data to be written directly into the SPI shift register. Be- cause this would corrupt any transfer in progress, a write collision error is generated instead.

  • Page 253: Serial Communication Interface (Sci)

    Freescale Semiconductor, Inc. 10.4 Serial Communication Interface (SCI) The SCI submodule contains two independent SCI systems. Each is a full-duplex uni- versal asynchronous receiver transmitter (UART). This SCI system is fully compatible with SCI systems found on other Freescale devices, such as the M68HC11 and M68HC05 families.
  • Page 254 Freescale Semiconductor, Inc. TRANSMITTER BAUD RATE CLOCK (WRITE ONLY) MDDR7 SCDR TX BUFFER MDDR5 10 (11) - BIT TX SHIFT REGISTER PIN BUFFER AND CONTROL PARITY GENERATOR FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCCR1 (CONTROL REGISTER 1) SCSR (STATUS REGISTER) TDRE SCI RX SCI INTERRUPT...
  • Page 255 Freescale Semiconductor, Inc. RECEIVER ÷ 16 BAUD RATE CLOCK 10 (11) - BIT RX SHIFT REGISTER DATA PIN BUFFER RECOVERY ALL ONES PARITY DETECT WAKE-UP LOGIC SCCR1 (CONTROL REGISTER 1) SCDR RX BUFFER (READ ONLY) SCSR (STATUS REGISTER) SCI TX REQUESTS SCI INTERRUPT REQUEST...

  • Page 256: Sci Status Register

    Freescale Semiconductor, Inc. SCCR1 contains a number of SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU16 can read and write this register at any time. The SCI can modify the RWU bit under certain circumstances.

  • Page 257: Receive Data Pins (Rxda, Rxdb)

    Freescale Semiconductor, Inc. Table 10-5 SCI Pins Mode SCI Function Port I/O Signal TXDA Serial data output from SCIA (TE = 1) PMC7 Transmit data TXDB Serial data output from SCIB (TE = 1) PMC5 RXDA Serial data input to SCIA (RE = 1) PMC6 Receive data RXDB...

  • Page 258: Serial Formats

    Freescale Semiconductor, Inc. 10.4.5.2 Serial Formats All data frames must have a start bit and at least one stop bit. Receiving and transmit- ting devices must use the same data frame format. The SCI provides hardware sup- port for both 10-bit and 11-bit frames. The M bit in SCCR1 specifies the number of bits per frame.

  • Page 259: Parity Checking

    Freescale Semiconductor, Inc. 10.4.5.4 Parity Checking The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and transmitted data. The PE bit in SCCR1 determines whether parity check- ing is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a frame is used for the parity function.

  • Page 260: Receiver Operation

    Freescale Semiconductor, Inc. The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is transmitted as a preamble to the following data frame. If TC = 0, the current opera- tion continues until the final bit in the frame is sent, then the preamble is transmitted.

  • Page 261: Idle-Line Detection

    Freescale Semiconductor, Inc. A receive time clock is used to control sampling and synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization of the re- ceive time clock with the incoming data stream. From this point on, data movement is synchronized with the MCU system clock.

  • Page 262: Receiver Wake-Up

    Freescale Semiconductor, Inc. In some applications, software overhead can cause a bit-time of logic level one to oc- cur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. When the ILIE bit in SCCR1 is set, an interrupt request is generated when the IDLE flag is set.

  • Page 263: Mcci Initialization

    Freescale Semiconductor, Inc. 10.5 MCCI Initialization After reset, the MCCI remains in an idle state. Several registers must be initialized be- fore serial operations begin. A general sequence guide for initialization follows. A. Global 1. Configure MMCR a. Write an interrupt arbitration number greater than zero into the IARB field. b.
  • Page 264 Freescale Semiconductor, Inc. MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10-24 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 265: General-Purpose Timer

    Freescale Semiconductor, Inc. SECTION 11 GENERAL-PURPOSE TIMER This section is an overview of the general-purpose timer (GPT) function. Refer to the GPT Reference Manual (GPTRM/AD) for complete information about the GPT mod- ule. 11.1 General The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required.

  • Page 266: Gpt Registers And Address Map

    Freescale Semiconductor, Inc. OC1/PGP3 IC1/PGP0 OC2/OC1/PGP4 IC2/PGP1 CAPTURE/COMPARE UNIT OC3/OC1/PGP5 IC3/PGP2 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PULSE ACCUMULATOR PCLK PRESCALER PWMA PWM UNIT PWMB BUS INTERFACE GPT BLOCK Figure 11-1 GPT Block Diagram 11.2 GPT Registers and Address Map The GPT programming model consists of a configuration register (GPTMCR), parallel I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2, TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL), pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,...

  • Page 267: Special Modes Of Operation

    Freescale Semiconductor, Inc. Refer to D.8 General-Purpose Timer for a GPT address map and register bit/field de- scriptions. Refer to 5.2.1 Module Mapping for more information about how the state of MM affects the system. 11.3 Special Modes of Operation The GPT module configuration register (GPTMCR) is used to control special GPT op- erating modes.

  • Page 268: Single-Step Mode

    Freescale Semiconductor, Inc. 11.3.3 Single-Step Mode Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP bit is asserted, the prescaler and the pulse accumulator stop counting and changes at input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP was set.

  • Page 269: Interrupts

    Freescale Semiconductor, Inc. Table 11-1 GPT Status Flags Flag Register Source Mnemonic Assignment IC1F TFLG1 Input capture 1 IC2F TFLG1 Input capture 2 IC3F TFLG1 Input capture 3 OC1F TFLG1 Output compare 1 OC2F TFLG1 Output compare 2 OC3F TFLG1 Output compare 3 OC4F TFLG1...
  • Page 270 Freescale Semiconductor, Inc. Table 11-2 GPT Interrupt Sources Source Vector Name Source Number Number — 0000 Adjusted channel IVBA : 0000 0001 Input capture 1 IVBA : 0001 0010 Input capture 2 IVBA : 0010 0011 Input capture 3 IVBA : 0011 0100 Output compare 1 IVBA : 0100...

  • Page 271: Pin Descriptions

    Freescale Semiconductor, Inc. Interrupt requests are asserted until associated status flags are cleared. Status flags must be cleared in a particular sequence. The status register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event oc- curs between the time that the register is read and the time that it is written, the asso- ciated flag is not cleared.

  • Page 272: Pulse-Width Modulation

    Freescale Semiconductor, Inc. 11.5.5 Pulse-Width Modulation Pulse-width modulation (PWMA/B) pins carry pulse-width modulator outputs. The modulators can be programmed to generate a periodic waveform of variable frequen- cy and duty cycle. PWMA can be used to output the clock selected as the input to the PWM counter.
  • Page 273 Freescale Semiconductor, Inc. SYSTEM CLOCK DIVIDER TO PULSE ACCUMULATOR EXT. TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR CPR2 CPR1 CPR0 TO CAPTURE/ COMPARE TIMER SELECT EXT. PWM UNIT SELECT EXT. PCLK SYNCHRONIZER AND DIGITAL FILTER PPR2 PPR1 PPR0 GPT PRE BLOCK Figure 11-2 Prescaler Block Diagram In the prescaler, the system clock is divided by a nine-stage divider chain.

  • Page 274: Capture/Compare Unit

    Freescale Semiconductor, Inc. The prescaler can be read at any time. In freeze mode the prescaler can also be writ- ten. Word accesses must be used to ensure coherency. If coherency is not needed byte accesses can be used. The prescaler value is contained in bits [8:0] while bits [15:9] are unimplemented and are read as zeros.
  • Page 275 Freescale Semiconductor, Inc. PCLK PRESCALER – DIVIDE BY SYSTEM 4, 8, 16, 32, 64, 128, 256 CLOCK TCNT (HI) TCNT (LO) 1 OF 8 SELECT 16-BIT FREE RUNNING CPR2 CPR1 CPR0 COUNTER INTERRUPT REQUESTS 16-BIT TIMER BUS FUNCTIONS IC1I PGP0 16-BIT LATCH IC1F BIT 0...
  • Page 276 Freescale Semiconductor, Inc. Edge-detection logic consists of control bits that enable edge detection and select a transition to detect. The EDGExA/B bits in timer control register 2 (TCTL2) determine whether the input capture functions detect rising edges only, falling edges only, or both rising and falling edges.

  • Page 277: Output Compare Functions

    Freescale Semiconductor, Inc. (PHI1) clock CAPTURE/COMPARE CLOCK TCNT $0101 $0102 EXTERNAL PIN SYNCHRONIZER OUTPUT CAPTURE REGISTER $0102 ICxF FLAG NOTES: PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 16/32 IC TIM Figure 11-4 Input Capture Timing Example An input capture occurs every time a selected edge is detected, even when the input capture status flag is set.

  • Page 278: Output Compare 1

    Freescale Semiconductor, Inc. 11.8.3.1 Output Compare 1 Output compare 1 can affect any or all of OC[5:1] when an output match occurs. In addition to allowing generation of multiple control signals from a single comparison op- eration, this function makes it possible for two or more output compare functions to control the state of a single OC pin.
  • Page 279 Freescale Semiconductor, Inc. INTERRUPT REQUESTS TMSK2 TFLG2 SYNCHRONIZER EDGE OVERFLOW & DETECT PACNT DIGITAL FILTER LOGIC 8-BIT COUNTER ENABLE PACTL INTERNAL DATA BUS PCLK TCNT OVERFLOW CAPTURE/COMPARE CLK PRESCALER 512 16/32 PULSE ACC BLOCK Figure 11-5 Pulse Accumulator Block Diagram In event counting mode, the counter increments each time a selected transition of the pulse accumulator input (PAI) pin is detected.

  • Page 280: Pulse-Width Modulation Unit

    Freescale Semiconductor, Inc. An interrupt request can be made when each of the status flags is set. However, op- eration of the PAI interrupt depends on operating mode. In event counting mode, an interrupt is requested when the edge being counted is detected. In gated mode, the request is made when the PAI input changes from active to inactive state.
  • Page 281 Freescale Semiconductor, Inc. 16-BIT DATA BUS PWMA REGISTER PWMB REGISTER PWMBUFA REGISTER PWMBUFB REGISTER "A" COMPARATOR "B" COMPARATOR PWMA PWMB LATCH LATCH ZERO DETECTOR ZERO DETECTOR "A" MULTIPLEXER "B" MULTIPLEXER [14:0] 16-BIT COUNTER FROM PRESCALER CLOCK 16/32 PWM BLOCK Figure 11-6 PWM Block Diagram The PWM unit has two operational modes.

  • Page 282: Pwm Counter

    Freescale Semiconductor, Inc. 11.11.1 PWM Counter The 16-bit counter in the PWM unit is similar to the timer counter in the capture/com- pare unit. During reset, the GPT is configured to use the system clock divided by two to drive the counter. Initialization software can reconfigure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin.
  • Page 283 Freescale Semiconductor, Inc. Data written to PWMA and PWMB is not used until the end of a complete cycle. This prevents spurious short or long pulses when register values are changed. The current duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PW- MBUFB).
  • Page 284 Freescale Semiconductor, Inc. GENERAL-PURPOSE TIMER M68HC16 Z SERIES 11-20 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 285 Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS Table A-1 Maximum Ratings Rating Symbol Value Unit 1, 2, 3 Supply Voltage – 0.3 to +6.5 1, 2, 3, 4, 5, 7 Input Voltage – 0.3 to +6.5 Instantaneous Maximum Current 1, 3, 5, 6 Single Pin Limit (applies to all pins) Operating Maximum Current 3, 5, 6, 7, 8...
  • Page 286 Freescale Semiconductor, Inc. Table A-2 Typical Ratings, 2.7 to 3.6V, 16.78-MHz Operation Rating Symbol Value Unit Supply Voltage °C Operating Temperature Supply Current µA LPSTOP, VCO off LPSTOP, External clock, max f Clock Synthesizer Operating Voltage DDSYN Supply Current DDSYN 4.194 MHz VCO on, maximum f µA 32.768 kHz VCO on, maximum f...
  • Page 287 Freescale Semiconductor, Inc. Table A-3 Typical Ratings, 5V, 16.78-MHz Operation Rating Symbol Value Unit Supply Voltage °C Operating Temperature Supply Current µA LPSTOP, VCO off LPSTOP, External clock, maximum f Clock Synthesizer Operating Voltage DDSYN Supply Current DDSYN VCO on, maximum f External Clock, maximum f DDSYN µA...
  • Page 288 Freescale Semiconductor, Inc. Table A-5 Typical Ratings, 25.17-MHz Rating Symbol Value Unit Supply Voltage °C Operating Temperature Supply Current µA LPSTOP, VCO off LPSTOP, External clock, max f 3.75 Clock Synthesizer Operating Voltage DDSYN Supply Current DDSYN VCO on, maximum f External Clock, maximum f DDSYN µA...
  • Page 289 Freescale Semiconductor, Inc. Table A-6 Thermal Characteristics Characteristic Symbol Value Unit Thermal Resistance Θ °C/W Plastic 132-Pin Surface Mount Plastic 144-Pin Surface Mount The average chip-junction temperature (T ) in C can be obtained from: × Θ where: = Ambient Temperature, °C Θ...
  • Page 290 Freescale Semiconductor, Inc. Table A-7 Low Voltage Clock Control Timing and V = 2.7 to 3.6 Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit PLL Reference Frequency Range MC68CM16Z1 PLL Reference Frequency Range MC68CK16Z1 MC68CK16Z4 System Frequency 16.78 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency...
  • Page 291 V = 0 Vdc, T to T DDSYN Characteristic Symbol Minimum Maximum Unit PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 System Frequency 16.78 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency 4 (f 16.78 Fast On-Chip PLL System Frequency...
  • Page 292 V = 0 Vdc, T to T DDSYN Characteristic Symbol Minimum Maximum Unit PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 System Frequency 20.97 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency 4 (f 20.97 Fast On-Chip PLL System Frequency...
  • Page 293 Long term (500 µs interval) –0.05 NOTES: 1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the MC68HC16Z3 requires a 4.194 MHz crystal reference.
  • Page 294 Freescale Semiconductor, Inc. Table A-11 Low Voltage 16.78-MHz DC Characteristics and V = 2.7 to 3.6Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Input High Voltage 0.7 (V + 0.3 Input Low Voltage – 0.3 0.2 (V Input Hysteresis —...
  • Page 295 Freescale Semiconductor, Inc. Table A-11 Low Voltage 16.78-MHz DC Characteristics (Continued) and V = 2.7 to 3.6Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit MC68CM16Z1/Z4 Power Dissipation — 2, 7 Input Capacitance All input-only pins — All input/output pins —...
  • Page 296 9, 10 Data Bus Mode Select Pull-Up Current µA — –120 –15 — 11, 12, 13 MC68HC16Z1 V Supply Current — µA — LPSTOP, crystal, VCO Off (STSIM = 0) — LPSTOP, external clock input frequency = maximum f 11, 12, 13...
  • Page 297 = 5.0 Vdc ± 10%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit MC68HC16Z1 RAM Standby Current > V µA Normal RAM operation – 0.5 V — − 0.5 V ≥ V ≥ V Transient condition + 0.5 V...
  • Page 298 9, 10 Data Bus Mode Select Pull-Up Current µA — –120 –15 — 11, 12, 13 MC68HC16Z1 V Supply Current — µA LPSTOP, crystal, VCO Off (STSIM = 0) — LPSTOP, external clock input frequency = maximum f — 11, 12, 13...
  • Page 299 = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit MC68HC16Z1 RAM Standby Current > V µA Normal RAM operation – 0.5 V — − 0.5 V ≥ V ≥ V Transient condition + 0.5 V...
  • Page 300 9, 10 Data Bus Mode Select Pull-Up Current µA — –120 –15 — 11, 12, 13 MC68HC16Z1 V Supply Current — µA LPSTOP, crystal, VCO Off (STSIM = 0) — LPSTOP, external clock input frequency = maximum f — 11, 12, 13...
  • Page 301 = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit MC68HC16Z1 RAM Standby Current > V µA Normal RAM operation – 0.5 V — − 0.5 V ≥ V ≥ V Transient condition + 0.5 V...
  • Page 302 Freescale Semiconductor, Inc. 13. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, MC68HC16Z2, and the MC68HC16Z3 requires a 4.194 MHz crystal reference. 14. The RAM module will not switch into standby mode as long as V does not exceed V by more than 0.5...
  • Page 303 Freescale Semiconductor, Inc. Table A-15 Low Voltage 16.78-MHz AC Timing and V = 2.7 to 3.6Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation — 16.78 MHz Clock Period 59.6 — ECLK Period — Ecyc External Clock Input Period —...
  • Page 304 Freescale Semiconductor, Inc. Table A-15 Low Voltage 16.78-MHz AC Timing (Continued) and V = 2.7 to 3.6Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In Invalid (Fast Cycle Hold) — CLDI CLKOUT Low to Data In High Impedance —...
  • Page 305 Freescale Semiconductor, Inc. Table A-16 16.78-MHz AC Timing = 5.0 Vdc ± 10 %, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation — 16.78 Clock Period 59.6 — ECLK Period — Ecyc External Clock Input Period 59.6 —...
  • Page 306 Freescale Semiconductor, Inc. Table A-16 16.78-MHz AC Timing (Continued) = 5.0 Vdc ± 10 %, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In Invalid (Fast Cycle Hold) — CLDI CLKOUT Low to Data In High Impedance —...
  • Page 307 Freescale Semiconductor, Inc. Table A-17 20.97-MHz AC Timing = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation — 20.97 Clock Period 47.7 — ECLK Period — Ecyc External Clock Input Period 47.7 —...
  • Page 308 Freescale Semiconductor, Inc. Table A-17 20.97-MHz AC Timing (Continued) = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In Invalid (Fast Cycle Hold) — CLDI CLKOUT Low to Data In High Impedance —...
  • Page 309 Freescale Semiconductor, Inc. Table A-18 25.17-MHz AC Timing = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation — 25.166 Clock Period 39.7 — ECLK Period — Ecyc External Clock Input Period 39.7 —...
  • Page 310 Freescale Semiconductor, Inc. Table A-18 25.17-MHz AC Timing (Continued) = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In Invalid (Fast Cycle Hold) — CLDI CLKOUT Low to Data In High Impedance —...
  • Page 311 Freescale Semiconductor, Inc. 3. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low dur- ing reset) do not pertain to an external reference applied while the PLL is enabled (MODCLK pin held high during reset).
  • Page 312 Freescale Semiconductor, Inc. CLKOUT 16 CLKOUT TIM Figure A-1 CLKOUT Output Timing Diagram EXTAL NOTE: TIMING SHOWN WITH RESPECT TO V LEVELS. PULSE WIDTH SHOWN WITH RESPECT TO 50% V 16 EXT CLK INPUT TIM Figure A-2 External Clock Input Timing Diagram ECLK NOTE: TIMING SHOWN WITH RESPECT TO V LEVELS.
  • Page 313 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[2:0] SIZ[1:0] DSACK0 DSACK1 DATA[15:0] BERR HALT BKPT ASYNCHRONOUS INPUTS IPIPE0 PHASE 1 PHASE 2 IPIPE1 16 RD CYC TIM Figure A-4 Read Cycle Timing Diagram M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-29 For More Information On This Product, Go to: www.freescale.com...
  • Page 314 Freescale Semiconductor, Inc. CLKOUT ADDR[23:20] FC[2:0] SIZ[1:0] DSACK0 DSACK1 DATA[15:0] BERR HALT BKPT IPIPE0 PHASE 1 PHASE 2 IPIPE1 16 WR CYC TIM Figure A-5 Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-30 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 315 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[2:0] SIZ[1:0] DATA[15:0] BKPT IPIPE0 PHASE 1 PHASE 2 IPIPE1 16 FAST RD CYC TIM Figure A-6 Fast Termination Read Cycle Timing Diagram M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-31 For More Information On This Product, Go to: www.freescale.com...
  • Page 316 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[1:0] SIZ[1:0] DATA[15:0] BKPT IPIPE0 PHASE 1 PHASE 2 IPIPE1 16 FAST WR CYC TIM Figure A-7 Fast Termination Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-32 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 317 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] DATA[15:0] DSACK0 DSACK1 BGACK IPIPE0 PHASE 1 PHASE 2 IPIPE1 16 BUS ARB TIM Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-33 For More Information On This Product, Go to: www.freescale.com...
  • Page 318 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] DATA[15:0] BGACK 16 BUS ARB TIM IDLE Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-34 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 319 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] DATA[15:0] BKPT IPIPE0 PHASE 1 PHASE 2 PHASE 1 PHASE 2 IPIPE1 SHOW CYCLE START OF EXTERNAL CYCLE NOTE: SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT-STATE INSERTION. 16 SHW CYC TIM Figure A-10 Show Cycle Timing Diagram M68HC16 Z SERIES...
  • Page 320 Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[2:0] SIZ[1:0] DATA[15:0] 16 CHIP SEL TIM Figure A-11 Chip-Select Timing Diagram RESET DATA[15:0], MODCLK, BKPT 16 RST/MODE SEL TIM Figure A-12 Reset and Mode Select Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-36 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 321 Freescale Semiconductor, Inc. Table A-19 Low Voltage 16.78-MHz Background Debug Mode Timing and V = 2.7 to 3.6Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit DSI Input Setup Time — DSISU DSI Input Hold Time — DSIH DSCLK Setup Time —...
  • Page 322 Freescale Semiconductor, Inc. Table A-21 20.97-MHz Background Debug Mode Timing = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit DSI Input Setup Time — DSISU DSI Input Hold Time — DSIH DSCLK Setup Time —...
  • Page 323 Freescale Semiconductor, Inc. CLKOUT FREEZE BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO 16 BDM SER COM TIM Figure A-13 Background Debug Mode Timing Diagram (Serial Communication) CLKOUT FREEZE IPIPE1/DSI 16 BDM FRZ TIM Figure A-14 Background Debug Mode Timing Diagram (Freeze Assertion) M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-39...
  • Page 324 Freescale Semiconductor, Inc. Table A-23 Low Voltage ECLK Bus Timing and V = 2.7 to 3.6 Vdc, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit ECLK Low to Address Valid — ECLK Low to Address Hold — ECLK Low to CS Valid (CS Delay) —...
  • Page 325 Freescale Semiconductor, Inc. Table A-24 16.78-MHz ECLK Bus Timing = 5.0 Vdc ± 10%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit ECLK Low to Address Valid — ECLK Low to Address Hold — ECLK Low to CS Valid (CS Delay) —...
  • Page 326 Freescale Semiconductor, Inc. Table A-25 20.97-MHz ECLK Bus Timing = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit ECLK Low to Address Valid — ECLK Low to Address Hold — ECLK Low to CS Valid (CS Delay) —...
  • Page 327 Freescale Semiconductor, Inc. Table A-26 25.17-MHz ECLK Bus Timing = 5.0 Vdc ± 5%, V and V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit ECLK Low to Address Valid — ECLK Low to Address Hold — ECLK Low to CS Valid (CS Delay) —...
  • Page 328 Freescale Semiconductor, Inc. CLKOUT ECLK ADDR[23:0] DATA[15:0] READ WRITE DATA[15:0] WRITE HC16 E CYCLE TIM Figure A-15 ECLK Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-44 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 329 Freescale Semiconductor, Inc. Table A-27 Low Voltage QSPI Timing and V = 2.7 to 3.6 Vdc, V = 0 Vdc, T to T DDSYN Function Symbol Unit Operating Frequency Master Slave Cycle Time Master qcyc Slave — Enable Lead Time Master lead Slave...
  • Page 330 Freescale Semiconductor, Inc. Table A-28 QSPI Timing = 5.0 Vdc ± 5% for 16.78 MHz, 10% for 20/25 MHz, V and V = 0 Vdc, T to T DDSYN Function Symbol Unit Operating Frequency Master Slave Cycle Time Master qcyc Slave —...
  • Page 331 Freescale Semiconductor, Inc. PCS[3:0] OUTPUT CPOL=0 OUTPUT CPOL=1 OUTPUT MISO MSB IN DATA LSB IN MSB IN INPUT MOSI MSB OUT DATA LSB OUT PORT DATA MSB OUT OUTPUT 16 QSPI MAST CPHA0 Figure A-16 QSPI Timing — Master, CPHA = 0 PCS[3:0] OUTPUT CPOL=0...
  • Page 332 Freescale Semiconductor, Inc. INPUT CPOL=0 INPUT CPOL=1 INPUT MISO MSB OUT DATA LSB OUT MSB OUT OUTPUT MOSI MSB IN DATA LSB IN MSB IN INPUT 16 QSPI SLV CPHA0 Figure A-18 QSPI Timing — Slave, CPHA = 0 INPUT CPOL=0 INPUT CPOL=1...
  • Page 333 Freescale Semiconductor, Inc. Table A-29 Low Voltage SPI Timing and V = 2.7 to 3.6 Vdc, V = 0 Vdc, T to T DDSYN Function Symbol Unit Operating Frequency Master Slave Cycle Time Master qcyc Slave — Enable Lead Time Master lead Slave...
  • Page 334 Freescale Semiconductor, Inc. Table A-30 SPI Timing = 5.0 Vdc ± 10% for 16.78 MHz, 5% for 20/25 MHz, V and V = 0 Vdc, T to T DDSYN Function Symbol Unit Operating Frequency Master Slave Cycle Time Master qcyc Slave —...
  • Page 335 Freescale Semiconductor, Inc. CPOL=0 OUTPUT CPOL=1 OUTPUT MISO MSB IN DATA LSB IN MSB IN INPUT MOSI MSB OUT DATA LSB OUT PORT DATA MSB OUT OUTPUT 16 MCCI MAST CPHA0 Figure A-20 SPI Timing — Master, CPHA = 0 CPOL=0 OUTPUT CPOL=1...
  • Page 336 Freescale Semiconductor, Inc. INPUT CPOL=0 INPUT CPOL=1 INPUT MISO MSB OUT DATA LSB OUT MSB OUT OUTPUT MOSI MSB IN DATA LSB IN MSB IN INPUT 16 MCCI SLV CPHA0 Figure A-22 SPI Timing — Slave, CPHA = 0 INPUT CPOL=0 INPUT CPOL=1...
  • Page 337 Freescale Semiconductor, Inc. Table A-31 General-Purpose Timer AC Characteristics Parameter Symbol Unit Operating Frequency Fclock 16.78 PCLK Frequency Fpclk 1/4 Fclock Pulse Width Input Capture PWtim 2/Fclock — — PWM Resolution — 2/Fclock — — IC/OC Resolution — 4/Fclock — —...
  • Page 338 Freescale Semiconductor, Inc. PHI1 PAEN EXT PIN (PAI) PACNT PAIF PAOVF NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. A = PAI SIGNAL AFTER THE SYNCHRONIZER. 3. B = “A” AFTER THE DIGITAL FILTER. 4.
  • Page 339 Freescale Semiconductor, Inc. PHI1 PHI1/4 PAEN EXT PIN (PAI) PACNT PAIF NOTES: 1. PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. PHI1/4 CLOCKS PACNT WHEN GT-PAIF IS ASSERTED. 3. A = PAI SIGNAL AFTER THE SYNCHRONIZER. 4.
  • Page 340 Freescale Semiconductor, Inc. PHI1 PHI1/4 EXT PIN (PAI) $FFFE $FFFF $0000 TCNT PACNT NOTES: 1. PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. TCNT COUNTS AS A RESULT OF PHI1/4; PACNT COUNTS WHEN TCNT OVERFLOWS FROM $FFFF TO $0000 AND THE CONDITIONED PAI SIGNAL IS ASSERTED.
  • Page 341 Freescale Semiconductor, Inc. PHI1 COMPARE/CAPTURE CLOCK OCx COMPARE $0102 REGISTER $0101 $0102 $0103 TCNT OCx MATCH OCxF EXT PIN (OCx) NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. WHEN THE TCNT MATCHES THE OCx COMPARE REGISTER, THE OCx FLAG IS SET FOLLOWED BY THE OCx PIN CHANGING STATE.
  • Page 342 Freescale Semiconductor, Inc. PHI1 COMPARE/CAPTURE CLOCK TCNT $0101 $0102 EXTERNAL PIN CONDITIONED INPUT $0102 CAPTURE REGISTER ICxF NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. THE CONDITIONED INPUT SIGNAL CAUSES THE CURRENT VALUE OF THE TCNT TO BE LATCHED BY THE ICx CAPTURE REGISTER.
  • Page 343 Freescale Semiconductor, Inc. BUS STATES PHI1 PDDRx EXTERNAL PIN (INPUT) CONDITIONED INPUT PDRx INTERNAL NEW DATA DATA BUS IMB READ CYCLE IMB READ CYCLE IMB READ CYCLE (READ BIT AS 1) (READ BIT AS 1) (READ BIT AS 0) NOTES: 1.
  • Page 344 Freescale Semiconductor, Inc. BUS STATES PHI1 INTERNAL DATA BUS PDRx EXTERNAL PIN (OUTPUT) CONDITIONED INPUT ICx COMPARE $0102 REGISTER PDDRX TCNT $0101 $0102 IMB WRITE CYCLE IMB WRITE CYCLE NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2.
  • Page 345 Freescale Semiconductor, Inc. BUS STATES PHI1 COMPARE/ COMPARE CLOCK TCNT $0101 $0102 $0103 TOCx $AOF3 FOCx OCxF (NOT SET) EXTERNAL PIN (OCx) IMB WRITE CYCLE NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. FORCE COMPARE Figure A-33 Force Compare (CLEAR) M68HC16 Z SERIES...
  • Page 346 Freescale Semiconductor, Inc. Table A-32 ADC Maximum Ratings Parameter Symbol Unit Analog Supply –0.3 Internal Digital Supply, with reference to V –0.3 Reference Supply, with reference to V –0.3 Differential Voltage –V –0.1 Differential Voltage –V –6.5 Differential Voltage –V –6.5 to V Differential Voltage...
  • Page 347 Freescale Semiconductor, Inc. Table A-33 Low Voltage ADC DC Electrical Characteristics (Operating) = 0 Vdc, ADCLK = 1.05 MHz, T within operating temperature range) Parameter Symbol Unit Analog Supply Internal Digital Supply Differential Voltage – 1.0 – Differential Voltage – 0.6 –...
  • Page 348 Freescale Semiconductor, Inc. Table A-35 5V ADC DC Electrical Characteristics (Operating) = 0 Vdc, ADCLK = 2.1 MHz, T to T Parameter Symbol Unit Analog Supply Internal Digital Supply Differential Voltage – 1.0 – Differential Voltage – 1.0 – Reference Voltage Low Reference Voltage High Differential Voltage –...
  • Page 349 Freescale Semiconductor, Inc. Table A-36 ADC AC Characteristics (Operating) = 5.0 Vdc ± 5% for 20/25 MHz, ± 10% for 16 MHz, V and V = 0 Vdc, within operating temperature range) Parameter Symbol Unit ADC Clock Frequency ADCLK 8-Bit Conversion Time µs 1.0 MHz 15.2...
  • Page 350 Freescale Semiconductor, Inc. Table A-37 Low Voltage ADC Conversion Characteristics (Operating) = 1.05 MHz) and V = 2.7 to 3.6 Vdc , V = 0 Vdc, T to T ADCLK Parameter Symbol Typical Unit 8-Bit Resolution 1 Count — — 8-Bit Differential Nonlinearity –0.5 —...
  • Page 351 Freescale Semiconductor, Inc. Table A-38 ADC Conversion Characteristics (Operating) = 5.0 Vdc ± 5% for 20/25 MHz, ± 10% for 16 MHz, V and V = 0 Vdc, T to T 0.5 MHz ≤ f ≤ 1.0 MHz, 2 clock input sample time) ADCLK Parameter Symbol...
  • Page 352 Freescale Semiconductor, Inc. IDEAL TRANSFER CURVE 8-BIT TRANSFER CURVE (NO CIRCUIT ERROR) INPUT IN mV, V – V = 3.072 V – +1/2 COUNT (6 mV) INHERENT QUANTIZATION ERROR – CIRCUIT-CONTRIBUTED +12 mV ERROR – +18 mV ABSOLUTE ERROR (1.5 8-BIT COUNTS) ADC 8-BIT ACCURACY LV Figure A-34 Low Voltage 8-Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS...
  • Page 353 Freescale Semiconductor, Inc. IDEAL TRANSFER CURVE 8-BIT TRANSFER CURVE (NO CIRCUIT ERROR) INPUT IN mV, V – V = 5.120 V – +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR – CIRCUIT-CONTRIBUTED +10mV ERROR – + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT) ADC 8-BIT ACCURACY Figure A-35 8-Bit ADC Conversion Accuracy M68HC16 Z SERIES...
  • Page 354 Freescale Semiconductor, Inc. IDEAL TRANSFER CURVE 10-BIT TRANSFER CURVE (NO CIRCUIT ERROR) INPUT IN mV, V – V = 3.072 V – +.5 COUNT (1.5 mV) INHERENT QUANTIZATION ERROR – CIRCUIT-CONTRIBUTED +10.5 mV ERROR – +12 mV ABSOLUTE ERROR (4 10-BIT COUNTS) ADC 10-BIT ACCURACY LV Figure A-36 Low Voltage 10-Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS...
  • Page 355 Freescale Semiconductor, Inc. IDEAL TRANSFER CURVE 10-BIT TRANSFER CURVE (NO CIRCUIT ERROR) INPUT IN mV, V – V = 5.120 V – +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR – CIRCUIT-CONTRIBUTED +10 mV ERROR – +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS) ADC 10-BIT ACCURACY Figure A-37 10-Bit ADC Conversion Accuracy M68HC16 Z SERIES...
  • Page 356 Freescale Semiconductor, Inc. ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-72 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 357 Freescale Semiconductor, Inc. APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z-series microcontrollers are available in both 132- and 144-pin packages. This appendix provides package pin assignment drawings, dimensional drawings, and ordering information. M68HC16 Z SERIES MECHANICAL DATA AND ORDERING INFORMATION USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 358 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK HC16Z1/CKZ1/CMZ1/Z2/Z3 132-PIN QFP Figure B-1 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES USER’S MANUAL For More Information On This Product,...
  • Page 359 Freescale Semiconductor, Inc. TXDA/PMC7 BR/CS0 ADDR1 FC2/CS5/PC2 ADDR2 FC1/CS4/PC1 ADDR3 FC0/CS3/PC0 ADDR4 CSBOOT ADDR5 DATA0 ADDR6 DATA1 ADDR7 DATA2 ADDR8 DATA3 ADDR9 DATA4 ADDR10 DATA5 ADDR11 DATA6 MC68HC16Z4 ADDR12 DATA7 MC68CK16Z4 ADDR13 DATA8 MMMMM ADDR14 DATA9 ATWLYYWW ADDR15 ADDR16 ADDR17 DATA10 ADDR18 DATA11...
  • Page 360 Freescale Semiconductor, Inc. 128X AC AC X=L, M, OR N VIEW AB PIN 1 VIEW AB IDENT BASE METAL Í Í Í Í Í Í Í Í Ç Ç Ç Í Í Í Í Ç Ç Ç PLATING SECTION AC–AC 0.002 L–M 0.016 L–M...
  • Page 361 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK HC16Z1/CKZ1/CMZ1/Z2/Z3 144-PIN QFP Figure B-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package M68HC16 Z SERIES MECHANICAL DATA AND ORDERING INFORMATION USER’S MANUAL For More Information On This Product,...
  • Page 362 Freescale Semiconductor, Inc. VRHP AS/PE5 AN5/PADA5 DS/PE4 AN4/PADA4 AVEC/PE2 AN3/PADA3 DSACK1/PE1 AN2/PADA2 DSACK0/PE0 AN1/PADA1 AN0/PADA0 ADDR0 VSSA DATA15 VDDA DATA14 DATA13 DATA12 DATA11 ADDR18 DATA10 ADDR17 ADDR16 ADDR15 MC68HC16Z4 DATA9 ADDR14 MC68CK16Z4 DATA8 ADDR13 MMMMM DATA7 ADDR12 DATA6 ATWLYYWW ADDR11 DATA5 ADDR10 DATA4...
  • Page 363 Freescale Semiconductor, Inc. 0.20 T L–M 0.20 T L–M 4X 36 TIPS PIN 1 IDENT X=L, M OR N 140X B1 V1 VIEW Y VIEW Y NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T.

  • Page 364: B.1 Obtaining Updated M68Hc16 Z-Series Mcu Mechanical Information

    (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z1 32 kHz 132-Pin –40 to +85°C 16 MHz SPMCK16Z1CFC16 PQFP MCK68HC16Z1CFC16 MCK16Z1CFC16B1 20 MHz SPMCK16Z1CFC20 MCK68HC16Z1CFC20 MCK16Z1CFC20B1 25 MHz SPMCK16Z1CFC25...
  • Page 365 (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z1 32 kHz 132-Pin –40 to +125°C 16 MHz SPMCK16Z1MFC16 PQFP MCK68HC16Z1MFC16 MCK16Z1MFC16B1 20 MHz SPMCK16Z1MFC20 MCK68HC16Z1MFC20 MCK16Z1MFC20B1 MC68HC16Z1 32 kHz 144-Pin –40 to +85°C...
  • Page 366 (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z1 4 MHz 2.7 V 144-Pin –40 to +85°C 16 MHz SPMCCM16Z1CPV16 TQFP MC68CM16Z1CPV16 MCCM16Z1CPV16B1 MC68HC16Z2 4 MHz 132-Pin –40 to +85°C 16 MHz...
  • Page 367 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z2 4 MHz 144-Pin –40 to +105°C 16 MHz (ROM) TQFP MC68HC16Z2VPV16...
  • Page 368 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z2 4 MHz 144-Pin –40 to +85°C 16 MHz SPMCM16Z2BCPV16 (No ROM) TQFP...
  • Page 369 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z3 4 MHz 132-Pin –40 to +105°C 16 MHz (ROM) PQFP MC68HC16Z3CFC16...
  • Page 370 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z3 4 MHz 132-Pin –40 to +85°C 16 MHz SPMCM16Z3RCFC16 (RTOS) PQFP...
  • Page 371 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z3 4 MHz 144-Pin –40 to +105°C 16 MHz SPMCM16Z3RVPV16 (RTOS) TQFP...
  • Page 372 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Package Crystal Operating Package Frequency Device Temperature Order Order Number Input Voltage Type (MHz) Quantity MC68HC16Z4 32 kHz 144-Pin –40 to +85°C 16 MHz SPMCK16Z4CPV16 TQFP MCK68HC16Z4CPV16...

  • Page 373: C.1 M68Mmds1632 Modular Development System

    Freescale Semiconductor, Inc. APPENDIX C DEVELOPMENT SUPPORT This section serves as a brief reference to Freescale development tools for M68HC16 Z-series microcontrollers. Information provided is complete as of the time of publication, but new systems and software are continually being developed. In addition, there is a growing number of third-party tools available.

  • Page 374: C.2 M68Mevb1632 Modular Evaluation Board

    • On-board V (+12 VDC) generation for MCU and flash EEPROM programming. • On-board wire-wrap area NOTE The MC68HC16Z1 and the MC68HC16Z2/Z3 both utilize the M68HC16MPFB, however, each MCU uses a different personality board (M68MPB16Z1 on the MC68HC16Z1; M68MPB16Z2/Z3 on the MC68HC16Z2/Z3).

  • Page 375: D.1 Central Processing Unit

    Freescale Semiconductor, Inc. APPENDIX D REGISTER SUMMARY This appendix contains address maps, register diagrams, and bit/field definitions for M68HC16 Z-series MCUs. More detailed information about register function is provid- ed in the appropriate sections of the manual. Except for central processing unit resources, information is presented in the intermod- ule bus address order shown in Table D-1.
  • Page 376 Freescale Semiconductor, Inc. BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D (A:B) ACCUMULATOR E INDEX REGISTER X INDEX REGISTER Y INDEX REGISTER Z STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION FIELD SK MAC MULTIPLIER REGISTER HR MAC MULTIPLICAND REGISTER IR...

  • Page 377: D.1.1 Condition Code Register

    Freescale Semiconductor, Inc. D.1.1 Condition Code Register CCR — Condition Code Register IP[2:0] PK[3:0] The CCR contains processor status flags, the interrupt priority field, and the program counter address extension field. The CPU16 has a special set of instructions that ma- nipulate the CCR.

  • Page 378: D.2 System Integration Module

    Freescale Semiconductor, Inc. D.2 System Integration Module Table D-2 shows the SIM address map. Table D-2 SIM Address Map Address $YFFA00 SIM Module Configuration Register (SIMCR) $YFFA02 SIM Test Register (SIMTR) $YFFA04 Clock Synthesizer Control Register (SYNCR) $YFFA06 Not Used Reset Status Register (RSR) $YFFA08 SIM Test Register E (SIMTRE)
  • Page 379 Freescale Semiconductor, Inc. Table D-2 SIM Address Map (Continued) Address $YFFA4E Chip-Select Option Address Register 0 (CSOR0) $YFFA50 Chip-Select Base Address Register 1 (CSBAR1) $YFFA52 Chip-Select Option Address Register 1 (CSOR1) $YFFA54 Chip-Select Base Address Register 2 (CSBAR2) $YFFA56 Chip-Select Option Address Register 2 (CSOR2) $YFFA58 Chip-Select Base Address Register 3 (CSBAR3) $YFFA5A...

  • Page 380: D.2.1 Sim Module Configuration Register

    Freescale Semiconductor, Inc. D.2.1 SIM Module Configuration Register SIMCR — SIM Module Configuration Register $YFFA00 EXOFF FRZSW FRZBM SHEN[1:0] SUPV IARB[3:0] RSVD RESET: DATA11 NOTES: 1. This bit must be left at zero. Pulling DATA11 high during reset ensures this bit remains zero. A one in this bit could allow the MCU to enter an unsupported operating mode.

  • Page 381: D.2.2 System Integration Test Register

    Freescale Semiconductor, Inc. MM — Module Mapping 0 = Internal modules are addressed from $7FF000 – $7FFFFF. 1 = Internal modules are addressed from $FFF000 – $FFFFFF. The logic state of the MM determines the value of ADDR23 for IMB module addresses. Because ADDR[23:20] are driven to the same state as ADDR19, MM must be set to one.

  • Page 382: D.2.4 Reset Status Register

    Freescale Semiconductor, Inc. W — Frequency Control (VCO) This bit controls a prescaler tap in the synthesizer feedback loop. Setting this bit in- creases the VCO speed by a factor of four. VCO relock delay is required. X — Frequency Control (Prescaler) This bit controls a divide by two prescaler that is not in the synthesizer feedback loop.

  • Page 383: D.2.5 System Integration Test Register E

    Freescale Semiconductor, Inc. POW — Power-Up Reset Reset caused by the power-up reset circuit. SW — Software Watchdog Reset Reset caused by the software watchdog circuit. HLT — Halt Monitor Reset Reset caused by the halt monitor. SYS — System Reset The CPU16 does not support this function.

  • Page 384: D.2.8 Port E Pin Assignment Register

    Freescale Semiconductor, Inc. NOTE When changing a port E pin from an output to an input, the pin will drive high for approximately four milliseconds. This ensures that the shared bus control signal will be in a negated state before the pin be- comes an input.

  • Page 385: D.2.10 Port F Data Direction Register

    Freescale Semiconductor, Inc. sponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of this data register returns the value at the pin only if the pin is config- ured as a discrete input.

  • Page 386: D.2.12 System Protection Control Register

    Freescale Semiconductor, Inc. D.2.12 System Protection Control Register SYPCR — System Protection Control Register $YFFA20 NOT USED SWT[1:0] BMT[1:0] RESET: MODCLK This register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written once following power-on or reset. Bits [15:8] are unimplemented and will always read zero.

  • Page 387: D.2.13 Periodic Interrupt Control Register

    Freescale Semiconductor, Inc. ) Divide Ratio Specified by SWP and SWT[1:0] Time-out Period ------------------------------------------------------------------------------------------------------------------------------- ------------ - The following equation calculates the time-out period for an externally input clock fre- quency on both slow and fast reference frequency devices, when f is equal to the system clock frequency.

  • Page 388: D.2.14 Periodic Interrupt Timer Register

    Freescale Semiconductor, Inc. PIV[7:0] — Periodic Interrupt Vector This field specifies the periodic interrupt vector number supplied by the SIM when the CPU16 acknowledges an interrupt request. D.2.14 Periodic Interrupt Timer Register PITR — Periodic Interrupt Timer Register $YFFA24 PITM[7:0] RESET: MODCLK Contains the count value for the periodic timer.

  • Page 389: D.2.15 Software Watchdog Service Register

    Freescale Semiconductor, Inc. D.2.15 Software Watchdog Service Register SWSR — Software Watchdog Service Register $YFFA26 NOT USED SWSR[7:0] RESET: NOTES: 1. This register is shown with a read value. This register can be read or written at any time. Bits [15:8] are unimplemented and will always read zero.
  • Page 390 Freescale Semiconductor, Inc. Table D-8 Pin Assignment Field Encoding CSxPA[1:0] Description Discrete output Alternate function Chip-select (8-bit port) Chip-select (16-bit port) NOTES: 1. Does not apply to the CSBOOT field. This register contains seven 2-bit fields that determine the function of corresponding chip-select pins.

  • Page 391: D.2.18 Chip-Select Base Address Register Boot

    Freescale Semiconductor, Inc. Table D-10 CSPAR1 Pin Assignments CSPAR1 Field Chip-Select Signal Alternate Signal Discrete Output CS10PA[1:0] CS10 ECLK ADDR23 CS9PA[1:0] ADDR22 CS8PA[1:0] ADDR21 CS7PA[1:0] ADDR20 CS6PA[1:0] ADDR19 NOTES: 1. On the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless externally driven.

  • Page 392: D.2.20 Chip-Select Option Register Boot

    Freescale Semiconductor, Inc. Each chip-select pin has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. CSBARBT contains the base address for selection of a boot memory device. Bit and field definitions for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
  • Page 393 Freescale Semiconductor, Inc. CSORBT and CSOR[0:10] contain parameters that support operations from external memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same. MODE — Asynchronous/Synchronous Mode 0 = Asynchronous mode is selected. 1 = Synchronous mode is selected, and used with ECLK peripherals. In asynchronous mode, chip-select assertion is synchronized with AS and DS.
  • Page 394 Freescale Semiconductor, Inc. Table D-15 DSACK Field Encoding Clock Cycles Required Wait States Inserted DSACK[3:0] Per Access Per Access 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Fast Termination 1111 — External DSACK External memories are purchased with guaranteed access times on speed (in nano- seconds).
  • Page 395 Freescale Semiconductor, Inc. SPACE[1:0] — Address Space Select Use this option field to select an address space for chip-select assertion or to configure a chip-select as an interrupt acknowledge strobe for an external device. The CPU16 normally operates in supervisor mode only, but interrupt acknowledge cycles take place in CPU space.

  • Page 396: D.2.22 Master Shift Registers

    Freescale Semiconductor, Inc. D.2.22 Master Shift Registers TSTMSRA — Test Module Master Shift Register A $YFFA30 Used for factory test only. TSTMSRB — Test Module Master Shift Register B $YFFA32 Used for factory test only. D.2.23 Test Module Shift Count Register TSTSC —...

  • Page 397: D.3 Standby Ram Module

    Freescale Semiconductor, Inc. D.3 Standby RAM Module Table D-19 shows the SRAM address map. Table D-19 SRAM Address Map Address $YFFB00 RAM Module Configuration Register (RAMMCR) $YFFB02 RAM Test Register (RAMTST) $YFFB04 RAM Array Base Address Register High (RAMBAH) $YFFB06 RAM Array Base Address Register Low (RAMBAL) NOTES: 1.

  • Page 398: D.3.2 Ram Test Register

    Freescale Semiconductor, Inc. D.3.2 RAM Test Register RAMTST — RAM Test Register $YFFB02 Used for factory test only. D.3.3 Array Base Address Register High RAMBAH — Array Base Address Register High (Z1, Z2, Z3, and Z4) $YFFB04 ADDR ADDR ADDR ADDR ADDR ADDR...

  • Page 399: D.4 Masked Rom Module

    Freescale Semiconductor, Inc. D.4 Masked ROM Module The MRM is used only in the MC68HC16Z2 and the MC68HC16Z3. Table D-21 shows the MRM address map. The reset states shown for the MRM registers are for the generic (blank ROM) ver- sions of the device.
  • Page 400 Freescale Semiconductor, Inc. BOOT — Boot ROM Control Reset state of BOOT is specified at mask time. This is a read-only bit. 0 = ROM responds to bootstrap word locations during reset vector fetch. 1 = ROM does not respond to bootstrap word locations during reset vector fetch. Bootstrap operation is overridden if STOP = 1 at reset.

  • Page 401: D.4.2 Rom Array Base Address Registers

    Freescale Semiconductor, Inc. D.4.2 ROM Array Base Address Registers ROMBAH — ROM Array Base Address Register High $YFF824 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR RESET: The reset value of the shaded bits is user specified, but the bits can be written after reset to change the base address.

  • Page 402: D.4.4 Rom Bootstrap Words

    Freescale Semiconductor, Inc. D.4.4 ROM Bootstrap Words ROMBS0 — ROM Bootstrap Word 0 $YFF830 NOT USED ZK[3:0] SK[3:0] PK[3:0] ROMBS1 — ROM Bootstrap Word 1 $YFF832 PC[15:0] ROMBS2 — ROM Bootstrap Word 2 $YFF834 SP[15:0] ROMBS3 — ROM Bootstrap Word 3 $YFF836 IZ[15:0] Typically, CPU16 reset vectors reside in non-volatile memory and are fetched when...

  • Page 403: D.5 Analog-To-Digital Converter Module

    Freescale Semiconductor, Inc. D.5 Analog-to-Digital Converter Module Table D-24 ADC Module Address Map Address $YFF700 ADC Module Configuration Register (ADCMCR) $YFF702 ADC Test Register (ADCTEST) $YFF704 Not Used $YFF706 Not Used Port ADA Data Register (PORTADA) $YFF708 Not Used $YFF70A Control Register 0 (ADCTL0) $YFF70C Control Register 1 (ADCTL1)

  • Page 404: D.5.1 Adc Module Configuration Register

    Freescale Semiconductor, Inc. D.5.1 ADC Module Configuration Register ADCMCR — ADC Module Configuration Register $YFF700 STOP NOT USED SUPV NOT USED RESET: ADCMCR controls ADC operation during low-power stop mode, background debug mode, and freeze mode. STOP — Low-Power Stop Mode Enable 0 = Normal operation 1 = Low-power operation STOP places the ADC in low-power state.

  • Page 405: D.5.4 Adc Control Register 0

    Freescale Semiconductor, Inc. PADA[7:0] — Port ADA Data Pins A read of PADA[7:0] returns the logic level of the port ADA pins. If an input is not at an appropriate logic level (that is, outside the defined levels), the read is indeterminate. Use of a port ADA pin for digital input does not preclude its simultaneous use as an analog input.

  • Page 406: D.5.5 Adc Control Register 1

    Freescale Semiconductor, Inc. Table D-27 Prescaler Output Minimum Maximum PRS[4:0] ADC Clock System Clock System Clock %00000 Reserved — — %00001 System Clock/4 2.0 MHz 8.4 MHz %00010 System Clock/6 3.0 MHz 12.6 MHz %00011 System Clock/8 4.0 MHz 16.8 MHz …...
  • Page 407 Freescale Semiconductor, Inc. Table D-28 ADC Conversion Mode SCAN MULT S8CM MODE Single 4-Conversion Single-Channel Sequence Single 8-Conversion Single-Channel Sequence Single 4-Conversion Multichannel Sequence Single 8-Conversion Multichannel Sequence Multiple 4-Conversion Single-Channel Sequences Multiple 8-Conversion Single-Channel Sequences Multiple 4-Conversion Multichannel Sequences Multiple 8-Conversion Multichannel Sequences CD:CA —...
  • Page 408 Freescale Semiconductor, Inc. Table D-29 Single-Channel Conversions (MULT = 0) S8CM Input Result Register RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] Reserved RSLT[0:3] RSLT[0:3] RSLT[0:3] ) / 2 RSLT[0:3] – Test/Reserved RSLT[0:3] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7]...
  • Page 409 Freescale Semiconductor, Inc. Table D-30 Multiple-Channel Conversions (MULT = 1) S8CM Input Result Register RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 Reserved RSLT0 Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT0 RSLT1 ) / 2 RSLT2 – Test/Reserved RSLT3 RSLT0 RSLT1 RSLT2 RSLT3...

  • Page 410: D.5.6 Adc Status Register

    Freescale Semiconductor, Inc. D.5.6 ADC Status Register ADCSTAT — ADC Status Register $YFF70E NOT USED CCTR[2:0] CCF[7:0] RESET: ADCSTAT contains information related to the status of a conversion sequence. SCF — Sequence Complete Flag 0 = Sequence not complete 1 = Sequence complete SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first conversion sequence when SCAN is set.
  • Page 411 Freescale Semiconductor, Inc. D.5.9 Left Justified, Unsigned Result Register LJURR — Left Justified, Unsigned Result Register $YFF730–$YFF73F 8/10 8/10 8/10 8/10 8/10 8/10 8/10 8/10 NOT USED Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolu- tion.

  • Page 412: D.6 Queued Serial Module

    Freescale Semiconductor, Inc. D.6 Queued Serial Module Table D-31 QSM Address Map Address $YFFC00 QSM Module Configuration Register (QSMCR) $YFFC02 QSM Test Register (QTEST) $YFFC04 QSM Interrupt Level Register (QILR) QSM Interrupt Vector Register (QIVR) $YFFC06 Not Used $YFFC08 SCI Control 0 Register (SCCR0) $YFFC0A SCI Control 1 Register (SCCR1) $YFFC0C...

  • Page 413: D.6.2 Qsm Test Register

    Freescale Semiconductor, Inc. STOP — Low-Power Stop Mode Enable 0 = QSM clock operates normally. 1 = QSM clock is stopped. When STOP is set, the QSM enters low-power stop mode. The system clock input to the module is disabled. While STOP is set, only QSMCR reads and writes are guar- anteed to be valid, but only writes to the QSPI RAM and other QSM registers are guar- anteed valid.

  • Page 414: D.6.4 Sci Control Register

    Freescale Semiconductor, Inc. ILQSPI[2:0] — Interrupt Level for QSPI When an interrupt request is made, the ILQSPI value determines the priority level of all QSPI interrupts. When a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU16 to determine whether to respond. ILQSPI must have a value in the range $0 (interrupts disabled) to $7 (highest priority).

  • Page 415: D.6.5 Sci Control Register 1

    Freescale Semiconductor, Inc. Writing a value of zero to SCBR disables the baud rate generator. There are 8191 dif- ferent bauds available. The baud value depends on the value for SCBR and the sys- tem clock, as used in the equation above. Table D-32 shows possible baud rates for a 16.78 MHz system clock.
  • Page 416 Freescale Semiconductor, Inc. ILT — Idle-Line Detect Type 0 = Short idle-line detect (start count on first one). 1 = Long idle-line detect (start count on first one after stop bit(s)). PT — Parity Type 0 = Even parity 1 = Odd parity PE —...

  • Page 417: D.6.6 Sci Status Register

    Freescale Semiconductor, Inc. D.6.6 SCI Status Register SCSR — SCI Status Register $YFFC0C NOT USED TDRE RDRF IDLE RESET: SCSR contains flags that show SCI operating conditions. These flags are cleared ei- ther by SCI hardware or by a read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR.

  • Page 418: D.6.7 Sci Data Register

    Freescale Semiconductor, Inc. NF — Noise Error 0 = No noise detected in the received data. 1 = Noise detected in the received data. FE — Framing Error 0 = No framing error detected in the received data. 1 = Framing error or break detected in the received data. PF —...

  • Page 419: D.6.9 Port Qs Pin Assignment Register/Data Direction Register

    Freescale Semiconductor, Inc. D.6.9 Port QS Pin Assignment Register/Data Direction Register PQSPAR — PORT QS Pin Assignment Register $YFFC16 DDRQS — PORT QS Data Direction Register $YFFC17 PQSPA6 PQSPA5 PQSPA4 PQSPA3 PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0 USED USED RESET:...

  • Page 420: D.6.10 Qspi Control Register 0

    Freescale Semiconductor, Inc. Table D-34 Effect of DDRQS on QSM Pin Function QSM Pin Mode DDRQS Bit Bit State Pin Function MISO Master DDQS0 Serial data input to QSPI Disables data input Slave Disables data output Serial data output from QSPI MOSI Master DDQS1...
  • Page 421 Freescale Semiconductor, Inc. WOMQ — Wired-OR Mode for QSPI Pins 0 = Pins designated for output by DDRQS operate in normal mode. 1 = Pins designated for output by DDRQS operate in open-drain mode. BITS[3:0] — Bits Per Transfer In master mode, when BITSE is set in a command RAM byte, BITS[3:0] determines the number of data bits transferred.

  • Page 422: D.6.11 Qspi Control Register 1

    Freescale Semiconductor, Inc. SPBR[7:0] — Serial Clock Baud Rate The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from two to 255 into SPBR[7:0]. The following equation determines the SCK baud rate: SCK Baud Rate ------------------------------------ -...

  • Page 423: D.6.12 Qspi Control Register 2

    Freescale Semiconductor, Inc. DSCKL[6:0] — Delay before SCK When the DSCK bit is set in a command RAM byte, this field determines the length of the delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip- select pins.

  • Page 424: D.6.13 Qspi Control Register 3

    Freescale Semiconductor, Inc. SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. SPCR2 is buffered. New SPCR2 values become effective only after com- pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location.

  • Page 425: D.6.14 Receive Data Ram

    Freescale Semiconductor, Inc. HMIE — HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled. 1 = HALTA and MODF interrupts enabled. HMIE enables interrupt requests generated by the HALTA status flag or the MODF status flag in SPSR. HALT —...

  • Page 426: D.6.15 Transmit Data Ram

    Freescale Semiconductor, Inc. D.6.15 Transmit Data RAM TR[0:F] — Transmit Data RAM $YFFD20 – $YFFD3F Data that is to be transmitted by the QSPI is stored in this segment. The CPU16 nor- mally writes one word of data into this segment for each queue command to be exe- cuted.
  • Page 427 Freescale Semiconductor, Inc. DT — Delay after Transfer 0 = Delay after transfer is 17 ÷ f 1 = SPCR1 DTL[7:0] specifies delay after transfer. DSCK — PCS to SCK Delay 0 = PCS valid to SCK delay is one-half SCK. 1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.

  • Page 428: D.7 Multichannel Communication Interface Module

    Freescale Semiconductor, Inc. D.7 Multichannel Communication Interface Module The MCCI is used only in the MC68HC16Z4 and the MC68CK16Z4. Table D-37 shows the MCCI address map. Table D-37 MCCI Address Map Address $YFFC00 MCCI Module Configuration Register (MMCR) $YFFC02 MCCI Test Register (MTEST) $YFFC04 SCI Interrupt Level Register (ILSCI) MCCI Interrupt Vector Register (MIVR)

  • Page 429: D.7.2 Mcci Test Register

    Freescale Semiconductor, Inc. STOP — Low-Power Stop Mode Enable 0 = MCCI clock operates normally. 1 = MCCI clock is stopped. When STOP is set, the MCCI enters low-power stop mode. The system clock input to the module is disabled. While STOP is set, only MMCR reads and writes are guaran- teed to be valid.

  • Page 430: D.7.4 Mcci Interrupt Vector Register

    Freescale Semiconductor, Inc. D.7.4 MCCI Interrupt Vector Register MIVR — MCCI Interrupt Vector Register $YFFC05 ILSCI INTV[7:2] INTV[1:0] RESET: The MIVR determines which three vectors in the exception vector table are to be used for MCCI interrupts. The SPI and both SCI interfaces have separate interrupt vectors adja- cent to one another.

  • Page 431: D.7.6 Mcci Pin Assignment Register

    Freescale Semiconductor, Inc. ILSPI[2:0] — Interrupt Level for SPI ILSPI[2:0] determine the interrupt request levels of SPI interrupts. Program this field to a value from $0 (interrupts disabled) through $7 (highest priority). If the interrupt- request level programmed in this field matches the interrupt-request level pro- grammed for one of the SCI interfaces and both request an interrupt simultaneously, the SPI is given priority.

  • Page 432: D.7.7 Mcci Data Direction Register

    Freescale Semiconductor, Inc. D.7.7 MCCI Data Direction Register MDDR — MCCI Data Direction Register $YFFC0A NOT USED DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 RESET: MDDR determines whether pins configured for general-purpose I/O are inputs or out- puts. MDDR affects both SPI function and I/O function. During reset, all MCCI pins are configured as inputs.

  • Page 433: D.7.8 Mcci Port Data Registers

    Freescale Semiconductor, Inc. D.7.8 MCCI Port Data Registers PORTMC — MCCI Port Data Register $YFFC0C PORTMCP — MCCI Port Pin State Register $YFFC0E NOT USED PMC7 PMC6 PMC5 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 RESET: Two registers are associated with port MCCI, the MCCI general-purpose I/O port. Pins used for general-purpose I/O must be configured for that function.
  • Page 434 Freescale Semiconductor, Inc. SCI Baud Rate ------------------------------------------- - × 32 SCBR[12:0] SCBR[12:0] -------------------------------------------------------------------------- - × 32 SCI Baud Rate Desired where SCBR[12:0] is in the range of one to 8191. Writing a value of zero to SCBR dis- ables the baud rate generator. There are 8191 different baud rates available. The baud value depends on the value for SCBR and the system clock, as used in the equa- tion above.
  • Page 435 Freescale Semiconductor, Inc. Bit 15 — Not Implemented LOOPS — Loop Mode 0 = Normal SCI operation, no looping, feedback path disabled. 1 = Test SCI operation, looping, feedback path enabled. The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When LOOPS is set, SCI transmitter output is fed back into the receive serial shifter.

  • Page 436: D.7.11 Sci Status Register

    Freescale Semiconductor, Inc. TE — Transmitter Enable 0 = SCI transmitter disabled (TXD pin can be used as I/O). 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter). RE — Receiver Enable 0 = SCI receiver disabled. 1 = SCI receiver enabled. RWU —...

  • Page 437: D.7.12 Sci Data Register

    Freescale Semiconductor, Inc. RDRF — Receive Data Register Full 0 = Receive data register is empty or contains previously read data. 1 = Receive data register contains new data. RAF — Receiver Active 0 = SCI receiver is idle. 1 = SCI receiver is busy. IDLE —...

  • Page 438: D.7.13 Spi Control Register

    Freescale Semiconductor, Inc. D.7.13 SPI Control Register SPCR — SPI Control Register $YFFC38 SPIE WOMP MSTR CPOL CPHA LSBF SIZE SPBR[7:0] RESET: The SPCR contains parameters for configuring the SPI. The register can be read or written at any time. SPIE —...

  • Page 439: D.7.14 Spi Status Register

    Freescale Semiconductor, Inc. SIZE — Transfer Data Size 0 = 8-bit data transfer. 1 = 16-bit data transfer. SPBR[7:0] — Serial Clock Baud Rate The SPI uses a modulus counter to derive the SCK baud rate from the MCU system clock.

  • Page 440: D.7.15 Spi Data Register

    Freescale Semiconductor, Inc. MODF — Mode Fault Flag 0 = Normal operation. 1 = Another SPI node requested to become the network SPI master while the SPI was enabled in master mode (SS input taken low). The SPI asserts MODF when the SPI is in master mode (MSTR = 1) and the SS input pin is negated by an external driver.

  • Page 441: D.8 General-Purpose Timer

    Freescale Semiconductor, Inc. D.8 General-Purpose Timer Table D-42 GPT Address Map Address $YFF900 GPT Module Configuration Register (GPTMCR) $YFF902 GPT Module Test Register (GPTMTR) $YFF904 GPT Interrupt Configuration Register (ICR) Port GP Data Direction Register $YFFE06 Port GP Data Register (PORTGP) (DDRGP) Output Compare 1 Action Mask Output Compare 1 Action Data Register...

  • Page 442: D.8.2 Gpt Test Register

    Freescale Semiconductor, Inc. STOP — Stop Clocks 0 = GPT clock operates normally. 1 = GPT clock is stopped. FRZ1 — Not Implemented FRZ0 — FREEZE Assertion Response 0 = Ignore IMB FREEZE signal. 1 = FREEZE the current state of the GPT. STOPP —...

  • Page 443: D.8.4 Port Gp Data Direction Register/Data Register

    Freescale Semiconductor, Inc. Table D-43 GPT Interrupt Sources Name Source Number Source Vector Number — 0000 Adjusted Channel IVBA : 0000 0001 Input Capture 1 IVBA : 0001 0010 Input Capture 2 IVBA : 0010 0011 Input Capture 3 IVBA : 0011 0100 Output Compare 1 IVBA : 0100...

  • Page 444: D.8.6 Timer Counter Register

    Freescale Semiconductor, Inc. OC1M[5:1] — OC1 Mask Field OC1M[5:1] correspond to OC[5:1]. 0 = Corresponding output compare pin is not affected by OC1 compare. 1 = Corresponding output compare pin is affected by OC1 compare. OC1D[5:1] — OC1 Data Field OC1D[5:1] correspond to OC[5:1].

  • Page 445: D.8.8 Input Capture Registers 1–3

    Freescale Semiconductor, Inc. Table D-44 PAMOD and PEDGE Effects PAMOD PEDGE Effect PAI falling edge increments counter PAI rising edge increments counter Zero on PAI inhibits counting One on PAI inhibits counting PCLKS — PCLK Pin State (Read Only) I4/O5 — Input Capture 4/Output Compare 5 0 = Output compare 5 enabled 1 = Input capture 4 enabled PACLK[1:0] —...

  • Page 446: D.8.10 Input Capture 4/Output Compare 5 Register

    Freescale Semiconductor, Inc. D.8.10 Input Capture 4/Output Compare 5 Register TI4/O5 — Input Capture 4/Output Compare 5 Register $YFF91C This register serves either as input capture register 4 or output compare register 5, de- pending on the state of I4/O5 in PACTL. It is reset to $FFFF. D.8.11 Timer Control Registers 1 and 2 TCTL1/TCTL2 —...
  • Page 447 Freescale Semiconductor, Inc. TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions. I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable 0 = IC4/OC5 interrupt disabled. 1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set. OCI[4:1] —...

  • Page 448: D.8.13 Timer Interrupt Flag Registers 1 And 2

    Freescale Semiconductor, Inc. D.8.13 Timer Interrupt Flag Registers 1 and 2 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1–2 $YFF922 I4/O5F OCF[4:1] ICF[3:1] PAOVF PAIF RESET: These registers show condition flags that correspond to GPT events. If the corre- sponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs. I4/O5F —...
  • Page 449 Freescale Semiconductor, Inc. FOC[5:1] — Force Output Compare FOC[5:1] correspond to OC[5:1]. 0 = Has no effect. 1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set. FOC[5:1] correspond to OC[5:1]. FPWMA/B — Force PWM Value 0 = PWM pin A/B is used for PWM functions;...

  • Page 450: D.8.15 Pwm Registers A/B

    Freescale Semiconductor, Inc. Table D-50 PWM Frequency Ranges Prescaler Tap SFA/B = 0 SFA/B = 1 [2:0] 16.78 MHz 20.97 MHz 25.17 MHz 16.78 20.97 25.17 16.78 MHz 20.97 MHz 25.17 MHz Div 2 = 8.39 MHz Div 2 = 10.5 MHz Div 2 = 12.6 MHz 32.8 kHz 41 kHz...

  • Page 451: D.8.18 Gpt Prescaler

    Freescale Semiconductor, Inc. D.8.18 GPT Prescaler PRESCL — GPT Prescaler $YFF92C UNUSED POWER ON RESET ONLY: The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000. M68HC16 Z SERIES REGISTER SUMMARY USER’S MANUAL D-77...
  • Page 452 Freescale Semiconductor, Inc. REGISTER SUMMARY M68HC16 Z SERIES D-78 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 453: E.1 Initialization Programs

    Freescale Semiconductor, Inc. APPENDIX E INITIALIZATION AND PROGRAMMING EXAMPLES This section contains basic initialization programs and several programming exercises using different M68HC16 Z-series modules. The purpose of these exercises is to pro- vide the designer and programmer with a means to shorten design time. All of the pro- grams were written to run on the M68HC16Z1EVB evaluation board.

  • Page 454: E.1.1 Equates.asm

    Freescale Semiconductor, Inc. E.1.1 EQUATES.ASM *DESCRIPTION :THIS IS A TABLE OF EQUATES FOR ALL M68HC16 Z-SERIES REGISTERS. ************************************************************************** ***** SIM MODULE REGISTERS ***** SIMMCR EQU $FA00 ;SIM MODULE CONFIGURATION REGISTER SIMTR EQU $FA02 ;SYSTEM INTEGRATION TEST REGISTER SYNCR EQU $FA04 ;CLOCK SYNTHESIZER CONTROL REGISTER EQU $FA07 ;RESET STATUS REGISTER...
  • Page 455 Freescale Semiconductor, Inc. ***** SRAM MODULE REGISTERS ***** RAMMCR EQU $FB00 ;RAM MODULE CONFIGURATION REGISTER RAMTST EQU $FB02 ;RAM TEST REGISTER RAMBAH EQU $FB04 ;RAM BASE ADDRESS HIGH REGISTER RAMBAL EQU $FB06 ;RAM BASE ADDRESS LOW REGISTER ***** MRM MODULE REGISTERS ***** MRMCR EQU $F820 ;MASKED ROM MODULE CONFIGURATION REGISTER...
  • Page 456 Freescale Semiconductor, Inc. EQU $FD2E ;SPI TXD.RAM 7 EQU $FD30 ;SPI TXD.RAM 8 EQU $FD32 ;SPI TXD.RAM 9 EQU $FD34 ;SPI TXD.RAM A EQU $FD36 ;SPI TXD.RAM B EQU $FD38 ;SPI TXD.RAM C EQU $FD3A ;SPI TXD.RAM D EQU $FD3C ;SPI TXD.RAM E EQU $FD3E ;SPI TXD.RAM F...
  • Page 457 Freescale Semiconductor, Inc. PACTL EQU $F90C ;PULSE ACCUMULATOR CONTROL REGISTER PACNT EQU $F90D ;PULSE ACCUMULATOR COUNTER TIC1 EQU $F90E ;INPUT CAPTURE REGISTER 1 TIC2 EQU $F910 ;INPUT CAPTURE REGISTER 2 TIC3 EQU $F912 ;INPUT CAPTURE REGISTER 3 TOC1 EQU $F914 ;OUTPUT COMPARE REGISTER 1 TOC2 EQU $F916...

  • Page 458: E.1.2 Org00000.Asm

    Freescale Semiconductor, Inc. E.1.2 ORG00000.ASM Title : ORG00000 Description : This file is included to set up the reset vector ($00000 - $00006). **************************************************************************** $0000 ;put the following reset vector ;information ;at address $00000 of the memory map DC.W $0010 ;zk=0, sk=1, pk=0 DC.W $0200...
  • Page 459 Freescale Semiconductor, Inc. DC.W Level 5 Interrupt Autovector DC.W Level 6 Interrupt Autovector DC.W Level 7 Interrupt Autovector DC.W Spurious Interrupt DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved) DC.W (Unassigned Reserved)
  • Page 460 Freescale Semiconductor, Inc. DC.W User Defined Interrupt Vector 21 DC.W User Defined Interrupt Vector 22 DC.W User Defined Interrupt Vector 23 DC.W User Defined Interrupt Vector 24 DC.W User Defined Interrupt Vector 25 DC.W User Defined Interrupt Vector 26 DC.W User Defined Interrupt Vector 27 DC.W User Defined Interrupt Vector 28...
  • Page 461 Freescale Semiconductor, Inc. DC.W ;131 User Defined Interrupt Vector 76 DC.W ;132 User Defined Interrupt Vector 77 DC.W ;133 User Defined Interrupt Vector 78 DC.W ;134 User Defined Interrupt Vector 79 DC.W ;135 User Defined Interrupt Vector 80 DC.W ;136 User Defined Interrupt Vector 81 DC.W ;137...
  • Page 462 Freescale Semiconductor, Inc. DC.W ;186 User Defined Interrupt Vector 131 DC.W ;187 User Defined Interrupt Vector 132 DC.W ;188 User Defined Interrupt Vector 133 DC.W ;189 User Defined Interrupt Vector 134 DC.W ;190 User Defined Interrupt Vector 135 DC.W ;191 User Defined Interrupt Vector 136 DC.W ;192...

  • Page 463: E.1.4 Initsys.asm

    Freescale Semiconductor, Inc. DC.W ;241 User Defined Interrupt Vector 186 DC.W ;242 User Defined Interrupt Vector 187 DC.W ;243 User Defined Interrupt Vector 188 DC.W ;244 User Defined Interrupt Vector 189 DC.W ;245 User Defined Interrupt Vector 190 DC.W ;246 User Defined Interrupt Vector 191 DC.W ;247...

  • Page 464: E.1.6 Initsci.asm

    MEVB. Several of these programs send status messages using the SCI in the QSM on the MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3. These programs can be made to function with SCIA in the MCCI on the MC68HC16Z4 and MC68CKZ4 as follows: •...

  • Page 465: E.2.1 Sim Programming Examples

    Freescale Semiconductor, Inc. E.2.1 SIM Programming Examples The following programming examples involve using the system integration module (SIM). The programs include: • Using ports E and F. • Setting up U1 and U3 RAM slots with two 32K X 8 RAM chips using chip selects. •...

  • Page 466: E.2.1.2 Example 2 - Using Chip-Selects

    Freescale Semiconductor, Inc. STAB DDRF ;Port F pins 0-7 as outputs (force 3-7 to 0) LDAB #$01 LDAA #$00 ***** Main Loop ***** START: STAB PORTF0 ;store counter into Port E data register STAA PORTF0 ;load A register with Port F data register START ;go back and start the counting again at zero ***** Exceptions/Interrupts...
  • Page 467 Freescale Semiconductor, Inc. #$3030 CSOR1 ;set Chip Select 1, lower byte, write only #$0303 CSBAR2 ;set Chip Select 2 to fire at base addr $30000 #$7830 CSOR2 ;set Chip Select 2, both bytes, read and write #$3FFF CSPAR0 ;set Chip Selects 0,1,2 to 16-bit ports ***** The Main Program *****...

  • Page 468: E.2.1.3 Example 3 - Changing Clock Frequencies

    Freescale Semiconductor, Inc. SEND_CH ;if TDR is not empty, go back to check it again CLRA SCDR ;transmit one ASCII character to the screen TC_LOOP: LDAB SCSR+1 ANDB #$80 ;test the TC bit (transfer complete) TC_LOOP ;continue to wait until TC is set ;finish sending out one character ***** Exceptions/Interrupts...
  • Page 469 Freescale Semiconductor, Inc. SCCR1 ;enable SCI receiver and transmitter LDAB #$01 TBZK ;point ZK at bank 1 (the SRAM) #$0000 ;for indexing the variables CNT and DLY $0000 ;loop counter $0002 ;delay counter ***** Main Program ***** MAIN: LDAB #$7F ;set clock speed to 16.777MHz STAB SYNCR...

  • Page 470: E.2.1.4 Example 4 - Software Watchdog, Periodic Interrupt And Autovector Demo

    Freescale Semiconductor, Inc. SEND_CH ;go send out the byte #$01 ;increment IX to point to the next byte SEND_STRING ;loop back and do next byte in string STRING_DONE: DELAY ;wait for a moment ;go back to whence we came SEND_CH: ;subroutine to send out one byte to SCI LDAA SCSR...
  • Page 471 Freescale Semiconductor, Inc. $0200 ;start program after interrupt table ***** Initialize ***** INIT: ;initialization stuff TEMP $0006 ;variable space used in hex to asc routine SCCNT $0004 ;stores the current number of seconds MNCNT $0002 ;stores the current number of minutes HRCNT $0000 ;stores the current number of hours...
  • Page 472 Freescale Semiconductor, Inc. CMPB #$20 NO_DOG ;choose which string start address to load #DOG_STRING ;COP caused the reset PRINT NO_DOG: LDX #NO_DOG_STR ;COP did not cause the reset PRINT: SEND_STRING ;print the string to the screen ANDP #$FF1F ;set interrupt priority mask level to 0 ***** The Main Program *****...
  • Page 473 Freescale Semiconductor, Inc. LDAA SCCNT,Z ADDA #$01 ;increment # of seconds ;decimal adjust A CMPA #$60 ;compare # of seconds to 60 MINUTES ;if # of sec=60, then branch to minute routine SCCNT,Z ;if # of sec<60, store new # of sec DISPLAY ;send new time to dummy terminal for display ;return to main loop &...
  • Page 474 Freescale Semiconductor, Inc. LDAB SCCNT,Z HEXTOASC ;convert hex number to ASCII and print LINE_FD: ;output a linefeed LDAB #$0A ;load ASCII number for line feed SEND_CH ;send character to terminal CARRIAGE: ;output a carriage return LDAB #$0D ;ASCII number for carriage return SEND_CH ;send character to terminal ;done with display routine...

  • Page 475: E.2.2 Cpu16 Programming Example

    Freescale Semiconductor, Inc. E.2.2 CPU16 Programming Example The following programming example involves using the CPU16 indexed and extended addressing modes. Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information on the CPU16. E.2.2.1 Example 5 - Indexed and Extended Addressing Description : This program demonstrates indexed and extended addressing.

  • Page 476: E.2.3 Qsm/Sci Programming Example

    Freescale Semiconductor, Inc. E.2.3 QSM/SCI Programming Example The following programming example involves using a port of the serial communication interface (SCI), one of the serial interfaces of the queued serial module (QSM), to dis- play a message on a dummy terminal. Refer to SECTION 9 QUEUED SERIAL MODULE for more information on the QSM...

  • Page 477: E.2.4 Gpt Programming Example

    Freescale Semiconductor, Inc. #$01 ;increment IX to point to the next byte SEND_STRING ;loop back and do next byte in string STRING_DONE: ;subroutine to implement delay between messages #$FFFF ;load accumulator E with the delay time ;set up the counter LOOP: DECW 0,Z ;decrement the counter...
  • Page 478 Freescale Semiconductor, Inc. has overflowed ten times. **************************************************************************** INCLUDE 'EQUATES.ASM' ;table of EQUates for common register ;addresses INCLUDE 'ORG00000.ASM' ;initialize reset vector INCLUDE 'ORG00008.ASM' ;initialize interrupt vectors We are choosing User Defined Interrupt Vector 9 (interrupt vector 64 at address $0080) to be the base vector number (VBA) for the GPT because the least significant nibble in the address must be a $0.
  • Page 479 Freescale Semiconductor, Inc. STAB TMSK2 ;& set the TCNT's prescale to sysclock/128 Set up Input Capture and Output Compare LDAB #$27 ;Input Captures STAB TCTL2 ;TIC1=either, TIC2=rise, TIC3=fall, TIC4=off LDAB #$01 ;Output Compares STAB TCTL1 ;TOC2=toggle, TOC3=off, TOC4=off, TOC5=off #$1000 ;set OC2 to toggle every time that TOC2 ;TCNT is #$1000...
  • Page 480 Freescale Semiconductor, Inc. ANDA #$01 ;check only the TDRE flag bit SEND_CH ;if TDR is not empty, go back to check it again LDAA #$00 ;clear A to send a full word to SCDR ($FFC0E) SCDR ;transmit one ASCII character to the screen TC_LOOP: LDAB SCSR+1...
  • Page 481 Freescale Semiconductor, Inc. PAOV_CNT,Z PAOV_DONE ;skip print routine if not finished ;counting down from ten #STRING_PAOV SEND_STRING ;print the message LDAB #$0A STAB PAOV_CNT,Z ;reload the counter so we can do it again PAOV_DONE: BCLR TFLG2,#$20 ;clear the PAOV flag bit ;all done! BDM: BGND...
  • Page 482 Freescale Semiconductor, Inc. INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E-30 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 483 Freescale Semiconductor, Inc. INDEX –A– port ADA data register (PORTADA) D-30 result registers 8-13 right justified, unsigned (RJURR) D-36 ABIU status register (ADCSTAT) 8-6, D-36 AC timing test register (ADCTEST) D-30 16.78 MHz A-21 special operating modes 20.97 MHz A-23 ADCMCR 8-1, 8-3, D-30 25.17 MHz...
  • Page 484 Freescale Semiconductor, Inc. pins Breakpoint -to-digital converter (ADC). See ADC acknowledge cycle 5-41 Arbitration exceptions 4-40 AS 4-41, 5-31, 5-40, 5-43, 5-45, 5-47, 5-54 hardware breakpoints 5-41 ASPC 7-2, 7-3, D-26 mode selection 5-52 Asserted (definition) operation 5-42 Asynchronous exceptions 4-39 Breakpoints 4-41...
  • Page 485 4-36 4-37 levels of interrupt priority 5-58 4-37 memory Coherency 11-10, 11-12 management Combined program and data space map organization MC68HC16Z1/CKZ1/CMZ1 3-20 program counter (PC) MC68HC16Z2/Z3 3-21 reference manual MC68HC16Z4/CKZ4 3-22 register model 4-2, Command RAM registers Comparator condition code register (CCR)
  • Page 486 Freescale Semiconductor, Inc. –D– –E– DAC capacitor array (C 8-22 5-60 DATA 5-31 ECLK 5-21 Data bus timing and size acknowledge (DSACK). See DSACK 5-24 16.78 MHz A-41 20.97 MHz A-42 mode selection 5-50 25.17 MHz A-43 signals (DATA) 5-31 low voltage A-40 frame 9-25,...
  • Page 487 Freescale Semiconductor, Inc. –G– clock input signal (PCLK) 11-1 input timing diagram A-28 Gain 8-19 off (EXOFF) bit Gated time accumulation mode 11-15 leakage 8-23 General-purpose timer (GPT). See GPT 11-1 multiplexing of analog signal sources 8-20 reset (EXT) address map D-67 EXTRST (external reset) 5-55...
  • Page 488 Freescale Semiconductor, Inc. control register (PACTL) 11-8, 11-14, IARB 11-16, D-70 GPT 11-6, D-68 counter register (PACNT) 11-14, D-70 MCCI 10-3, D-55 -width modulation registers QSM 9-3, D-39 counter register (PWMCNT) 11-18 SIM 5-3, 5-59, 11-14 buffer registers (PWMBUFA/PWMBUFB) ICD16/ICD32 C-2 D-76 D-74 control register C (PWMC)
  • Page 489 Freescale Semiconductor, Inc. –L– Instruction execution model 4-35 fetches Leakage error 8-23 pipeline 4-35 Length of delay after transfer (DTL) D-49 set for CPU16 4-11 Level-sensitivity 5-58 timing 4-36 LJSRR D-36 Intermodule bus (IMB) 3-2, 11-1 LJURR D-37 Internal LOCK 7-3, D-26 error (BERR) 5-24, 5-25...
  • Page 490 (ILSCIA/B) D-55 Modulus counter 9-26, 10-18 10-4 Monotonicity MOSI 9-16, 9-20 132-pin assignment package MPAR 10-2, 10-4, D-57 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 3-7, MC68HC16Z4/CKZ4 3-9, 144-pin assignment package address map D-25 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 3-8, array address mapping MC68HC16Z4/CKZ4 3-10, features address maps...
  • Page 491 Freescale Semiconductor, Inc. Multichannel 1 (single comparison operation) 11-14 communication interface module (MCCI). See MCCI flags (OCF) D-74 10-1 functions 11-13, 11-14 conversion (MULT) D-32 interrupt enable (OCI) bit D-73 Multimaster operation mode bits/output compare level bits (OM/OL) Multiple D-72 -channel conversion D-35 status flag (OCxF) bit...
  • Page 492 Freescale Semiconductor, Inc. characteristics 3-11 PSHM considerations 8-14 PT 9-26, 10-19, D-42, D-61 electrical state 5-53 D-14 function 5-53 PULM reset states 5-54 Pulse Pipeline multiplexing 4-41 accumulator 11-1 PIRQL D-13 block diagram 11-15 PITM 5-28, D-14 clock PITR 5-28, D-14 select (PACLK) D-71...
  • Page 493 Freescale Semiconductor, Inc. registers — master, CPHA = 0/CPHA = 1 A-47 command RAM (CR) D-52 — slave, CPHA = 0/CPHA = 1 A-48 global registers low voltage A-45 interrupt QTEST 9-2, D-39 level register (QILR) 9-2, D-39 Queue pointers vector register (QIVR) 9-2, D-39 completed queue pointer (CPTQP)
  • Page 494 S 4-4, Select eight-conversion sequence mode (S8CM) D-32 S8CM D-32 Send break (SBK) 9-27, 10-20, D-42, D-62 Sample Separate program and data space map capacitor MC68HC16Z1/CKZ1/CMZ1 3-23 time MC68HC16Z2/Z3 3-24 time selection (STS) field D-31 MC68HC16Z4/CKZ4 3-25 8-13 Sequence complete flag (SCF)
  • Page 495 Freescale Semiconductor, Inc. Signed fractions block diagram (with PIT) 5-25 spurious interrupt monitor 5-25 address map system block diagram clock bus operation 5-36 block diagram chip-selects 5-61 protection 5-24 external bus interface (EBI) 5-29 system clock features synthesizer operation functional blocks SIMCR 5-2, 8-3, halt monitor 5-25...
  • Page 496 Freescale Semiconductor, Inc. low voltage A-49 Synchronous exceptions 4-39 transfer SYNCR 5-5, data flow 10-5 Synthesizer lock flag (SLOCK) size and direction 10-11 SYPCR D-12 write collision 10-12 SPI finished interrupt enable (SPIFIE) D-50 System SPIF D-51, D-65 clock SPIFIE D-50 output (CLKOUT) 5-36 SPSR 10-6, D-50,...
  • Page 497 Freescale Semiconductor, Inc. –W– data (TXD) pin — QSM 9-25 (TXDA/B) pins — MCCI 10-17 register empty (TDRE) flag WAIT 7-3, D-26 MCCI 10-19, D-62 Wait states field (WAIT) D-26 QSM 9-27, D-43 WAKE 9-30, 10-22, D-42, D-61 enable (TE) Wakeup MCCI 10-4, 10-13, 10-19, D-62...
  • Page 498 Freescale Semiconductor, Inc. M68HC16 Z SERIES I-16 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 499 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...
  • Page 500 Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7...
  • Page 501 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: MC68CK16Z1CAG16 MC68HC16Z1CAG16 MC68HC16Z1CAG20 MC68HC16Z1CAG25 MC68HC16Z1CEH16 MC68HC16Z1CEH20 MC68HC16Z1CEH25 MC68HC16Z1MAG16 MC68HC16Z1MEH16 MC68HC16Z1VEH16...

This manual is also suitable for:

Mc68hc16z4Mc68ck16z1Mc68ck16z4Mc68cm16z1Mc68hc16z2Mc68hc16z3

Table of Contents