Prescaler - NXP Semiconductors MC9S08SU16 Reference Manual

Functional Description
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the system clock or an external clock. This clock input
is defined by chip integration. Refer to chip specific documentation for further
information. Due to FTM hardware implementation limitations, the frequency of the
fixed frequency clock must not exceed the system clock frequency.
The external clock passes through a synchronizer clocked by the system clock to ensure
that counter transitions are properly aligned to system clock transitions. Therefore, to
meet the Nyquist criteria and account for jitter, the frequency of the external clock source
must not exceed 1/4 of the system clock frequency.

19.5.2 Prescaler

The selected counter clock source passes through a prescaler that is a 7-bit counter. The
value of the prescaler is selected by the PS[2:0] bits. The following figure shows an
example of the prescaler counter and FTM counter.
EPWM
PS[2:0] = 001
MODH:L = 0x0003
selected input clock
prescaler counter
FTM counter
19.5.3 Counter
The FTM has a 16-bit counter that is used by the channels either for input or output
modes. The FTM counter clock is the selected clock divided by the prescaler (see
Prescaler).
The FTM counter has these modes of operation:
• up counting (see
• up-down counting (see
330
1 0 1 0 1
0 2
1
Figure 19-3. Example of the prescaler counter
Up counting)
Up-down counting)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
0 1 0 1 0 1 0 1
2
3 0 1
0 1 0 1 0
3 0 1
NXP Semiconductors