Status And Control Register 3 (Adcx_Sc3) - NXP Semiconductors MC9S08SU16 Reference Manual

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Field
0
Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO.
1
Indicates that ADC result FIFO is full and next conversion will override old data in case of no read
action.
REFSEL
Voltage Reference Selection
Selects the voltage reference source used for conversions.
00
Default voltage reference pin pair (V
01
Analog supply pin pair (V
10
Reserved.
11
Reserved - Selects default voltage reference (V

17.4.3 Status and Control Register 3 (ADCx_SC3)

ADC_SC3 selects the mode of operation, clock source, clock divide, and configure for
low power or long sample time.
Address: Base address + 2h offset
Bit
7
Read
ADLPC
Write
Reset
0
Field
7
Low-Power Configuration
ADLPC
ADLPC controls the speed and power configuration of the successive approximation converter. This
optimizes power consumption when higher sample rates are not required.
0
High speed configuration.
1
Low power configuration:The power is reduced at the expense of maximum clock speed.
6–5
Clock Divide Select
ADIV
ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
00
Divide ration = 1, and clock rate = Input clock.
01
Divide ration = 2, and clock rate = Input clock ÷ 2.
10
Divide ration = 3, and clock rate = Input clock ÷ 4.
11
Divide ration = 4, and clock rate = Input clock ÷ 8.
4
Long Sample Time Configuration
ADLSMP
ADLSMP selects between long and short sample time. This adjusts the sample period to allow higher
impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs.
Longer sample times can also be used to lower overall power consumption when continuous conversions
are enabled if high conversion rates are not required.
NXP Semiconductors
ADCx_SC2 field descriptions (continued)
REFH
/V
).
DDA
SSA
6
5
ADIV
ADLSMP
0
0
ADCx_SC3 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 17 Analog-to-digital converter (ADC)
Description
/V
).
REFL
/V
) pin pair.
REFH
REFL
4
3
MODE
0
0
Description
2
1
ADICLK
0
0
0
0
265

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