External Mux Selection Register (Xbar_Extmux) - NXP Semiconductors MC9S08SU16 Reference Manual

Absolute
address
(hex)
18D6 XBAR Selection Register (XBAR_SEL6)
18D7 XBAR Selection Register (XBAR_SEL7)
18D8 XBAR Selection Register (XBAR_SEL8)
18D9 XBAR Selection Register (XBAR_SEL9)
18DA XBAR Selection Register (XBAR_SEL10)
18DB XBAR Selection Register (XBAR_SEL11)
18DC XBAR Selection Register (XBAR_SEL12)
18DD XBAR Selection Register (XBAR_SEL13)
18DE XBAR Selection Register (XBAR_SEL14)
18DF XBAR Selection Register (XBAR_SEL15)

24.4.1 External Mux Selection Register (XBAR_EXTMUX)

Address: 0h base + 6h offset = 6h
Bit 7
Read
Write
Reset
0
Field
7–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 External mux selection 2 for PWM channels
SEL2
0 PWM output channel 4.
1 PWM output channel 5.
1 External mux selection 1 for PWM channels
SEL1
0 PWM output channel 2.
1 PWM output channel 3.
0 External mux selection 0 for PWM channels
SEL0
0 PWM output channel 0.
1 PWM output channel 1.
NXP Semiconductors
XBAR memory map (continued)
Register name
6 5
0
0 0
XBAR_EXTMUX field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 24 Inter-peripheral Crossbar Switch (XBAR)
Width
Access
(in bits)
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
4 3
SEL2
0 0
Description
Section/
Reset value
page
02h 24.4.2/434
02h 24.4.2/434
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02h 24.4.2/434
02h 24.4.2/434
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02h 24.4.2/434
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2 1
SEL1 SEL0
0 0
0
0
433