Memory Map/Register Definitions - NXP Semiconductors MC9S08SU16 Reference Manual

• If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on
COUT due to the fact that COUT (which is crossing clock domain boundaries) must
be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.

18.10 Memory Map/Register Definitions

Address offsets are in terms of bytes for the S08 architecture.
Absolute
address
(hex)
68 CMP Control Register 0 (CMP_CR0)
69 CMP Control Register 1 (CMP_CR1)
6A CMP Filter Period Register (CMP_FPR)
6B CMP Status and Control Register (CMP_SCR)
6C DAC Control Register (CMP_DACCR)
6D MUX Control Register (CMP_MUXCR)
6E MUX Pin Enable Register (CMP_MUXPE)
18.10.1 CMP Control Register 0 (CMP_CR0)
Address: 68h base + 0h offset = 68h
Bit 7
Read 0
Write
Reset 0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6–4 Filter Sample Count
FILTER_CNT
These bits represent the number of consecutive samples that must agree prior to the comparator ouput
filter accepting a new output state. For information regarding filter programming and latency reference the
Functional Description.
NXP Semiconductors
CMP memory map
Register name
6 5
FILTER_CNT
0 0
CMP_CR0 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 18 Chip-specific ACMP information
Width
Access
(in bits)
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
4 3
0 0
Description
Section/
Reset value
page
00h 18.10.1/295
00h 18.10.2/296
00h 18.10.3/297
00h 18.10.4/298
00h 18.10.5/299
00h 18.10.6/300
00h 18.10.7/301
2 1
0
HYSTCTR
0 0
0
0
295