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14.6.4 VDDF
VDDF is the 2.8 V regulator (VREG
NVM block. VDDF is not pinned out because no external decoupling capacitor is
required.
14.6.5 VDD1.8
VDD1.8 is the 1.8 V regulator (VREG
digital logics including CPU and RAM. VDD1.8 is not pinned out because no external
decoupling capacitor is required.
14.7 Memory map and register definition
This section includes the module memory map and detailed descriptions of all registers.
Absolute
address
(hex)
1850
Control Register (PMC_CTRL)
1851
Reset Flags Register (PMC_RST)
Temperature Control and Status Register
1852
(PMC_TPCTRLSTAT)
1853
Temperature Offset Step Trim Register (PMC_TPTM)
1854
RC Oscillator Offset Step Trim Register (PMC_RC20KTRM)
Low Voltage Control and Status Register 1 (system 5 V)
1855
(PMC_LVCTLSTAT1)
Low Voltage Control and Status Register 2 (VREFH)
1856
(PMC_LVCTLSTAT2)
1857
VREFH Configuration Register (PMC_VREFHCFG)
VREFH Low Voltage Warning (LVW) Configuration Register
1858
(PMC_VREFHLVW)
1859
Status Register (PMC_STAT)
NXP Semiconductors
) output. It is the power supply of the on-chip
VDDF
) output. It is the power supply of the on-chip
VDD
PMC memory map
Register name
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 14 Power Management Controller (PMC)
Width
Access
Reset value
(in bits)
8
R/W
See section
8
R/W
See section
8
R/W
8
R/W
See section
8
R/W
8
R/W
See section
8
R/W
See section
8
R/W
See section
8
R/W
8
R/W
Section/
page
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02h
14.7.9/228
04h
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