Dac Control Register (Cmp_Daccr) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. In STOP
mode, CFF is level senstive and as long as the COUT is low CFF will be set in STOP mode. The CFF bit
is cleared by writing a logic one to the bit.
0 Falling edge on COUT has not been detected.
1 Falling edge on COUT has occurred.
0 Analog Comparator Output
COUT
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.

18.10.5 DAC Control Register (CMP_DACCR)

Address: 68h base + 4h offset = 6Ch
Bit 7
Read
DACEN
Write
Reset
0
Field
7 DAC Enable
DACEN
This bit is used to enable the DAC. When the DAC is disabled, it is powered down to conserve power.
0 DAC is disabled.
1 DAC is enabled.
6 Supply Voltage Reference Source Select
VRSEL
0 V
in1
1 V
in2
VOSEL DAC Output Voltage Select
This bit selects an output voltage from one of 64 distinct levels.
DACO = (Vin/64) * (VOSEL[5:0] + 1), so the DACO range is from Vin/64 to Vin.
NXP Semiconductors
CMP_SCR field descriptions (continued)
6 5
VRSEL
0 0
CMP_DACCR field descriptions
is selected as resistor ladder network supply reference Vin.
is selected as resistor ladder network supply reference Vin.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 18 Chip-specific ACMP information
Description
4 3
VOSEL
0 0
Description
2 1
0 0
0
0
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