Pwm Counter Register: High (Pwm_Cntrh) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
CNTR7_0 Counter 7:0

26.4.10 PWM Counter Register: High (PWM_CNTRH)

This read-only register, together with CNTRL, displays the state of the 15-bit PWM
counter. Reserved bit 7, cannot be modified. It is read as zero. Reading the CNTRL
causes an internal hold register to be updated with the CNTRH value. Reading the
CNTRH reads this internal hold register. Always read the lower byte before reading the
upper byte in order to guarantee a coherent 15-bit value is read.
Address: 40h base + 9h offset = 49h
Bit 7
Read 0
Write
Reset
0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
CNTR14_8 Counter 14:8
26.4.11 PWM Counter Register: Low (PWM_CMODL)
The 15-bit unsigned value written to this buffered, read/write register defines the PWM
period in PWM clock periods. Reserved bit 15 cannot be modified. It is read as zero.
The PWM counter modulo register is buffered. The value
written does not take effect until the LDOK bit is set and the
next PWM load cycle begins. Reading CMOD reads the value
in a buffer. It is not necessarily the value the PWM generator is
currently using.
Address: 40h base + Ah offset = 4Ah
Bit 7
Read
Write
Reset 0
NXP Semiconductors
PWM_CNTRL field descriptions
6 5
0 0
PWM_CNTRH field descriptions
NOTE
6 5
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Description
4 3
CNTR14_8
0 0
Description
4 3
CMOD7_0
0 0
2 1
0 0
2 1
0 0
0
0
0
0
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