System Options Register 2 (Sim_Sopt2) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition

9.8.6 System Options Register 2 (SIM_SOPT2)

This register may be read and written at any time.
Address: 1800h base + 5h offset = 1805h
Bit 7
Read
ESFC
Write
Reset 0
Field
7 Enable Stalling Flash Controller
ESFC
Enables stalling flash controller when flash is busy. When software needs to access the flash memory
while a flash memory resource is being manipulated by a flash command, software can enable a stall
mechanism to avoid a read collision. The stall mechanism allows software to execute code from the same
block on which flash operations are being performed. However, software must ensure the sector the flash
operations are being performed on is not the same sector from which the code is executing. ESFC
enables the stall mechanism. This bit must be set only just before the flash operation is executed and
must be cleared when the operation completes.
0 Disable stalling flash controller when flash is busy.
1 Enable stalling flash controller when flash is busy.
6 Write Protection for XBAR registers
WPXB
This field configures the write-protection for XBAR registers
0 XBAR registers are writable.
1 XBAR registers are not writable.
5–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
BUSREF BUS Output select
This bit enables bus clock output on PTB7 via an optional prescalar.
000 Bus.
001 Bus divided by 2.
010 Bus divided by 4.
011 Bus divided by 8.
100 Bus divided by 16.
101 Bus divided by 32.
110 Bus divided by 64.
111 Bus divided by 128.
110
6 5
WPXB
0 0
SIM_SOPT2 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0
0 0
Description
2 1
BUSREF
0 0
NXP Semiconductors
0
0