NXP Semiconductors MC9S08QL8 MCU Series Reference Manual
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NXP Semiconductors MC9S08QL8 MCU Series Reference Manual

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MC9S08QL8 MCU Series Reference Manual
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MC9S08QL8
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Rev. 1
07/2018
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors
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Summary of Contents for NXP Semiconductors MC9S08QL8 MCU Series

  • Page 1 MC9S08QL8 MCU Series Reference Manual Covers: MC9S08QL8 MC9S08QL4 MC9S08QL8RM Rev. 1 07/2018 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 2 The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 06/2018 Initial creation. Removed blank pages in the chapters. 07/2018 Updated PTA and PTC registers. All rights reserved. © 2018 NXP B.V. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 3: Table Of Contents

    Chapter 16 Development Support ....... . . 225 MC9S08QL8 MCU Series Reference Manual, Rev. 1...
  • Page 4 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 5 3.6.5 Stop Modes in Low Power Run Mode ................31 Mode Selection ..........................31 3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes .........34 Chapter 4 Memory MC9S08QL8 Series Memory Map ....................37 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 6 5.8.5 System Options Register 2 (SOPT2) ................69 5.8.6 System Device Identification Register (SDIDH, SDIDL) ..........70 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ......71 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ......72 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 7 Programmer’s Model and CPU Registers ..................96 8.2.1 Accumulator (A) .......................96 8.2.2 Index Register (H:X) ......................96 8.2.3 Stack Pointer (SP) ......................97 8.2.4 Program Counter (PC) ......................97 8.2.5 Condition Code Register (CCR) ..................97 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 8 10.2.2 Analog Ground (V ) ....................126 10.2.3 Voltage Reference High (V ) ...................126 REFH 10.2.4 Voltage Reference Low (V ) ..................126 REFL 10.2.5 Analog Channel Inputs (ADx) ..................126 10.3 Register Definition ........................126 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 9 11.4.1 Operational Modes ......................157 11.4.2 Mode Switching ......................159 11.4.3 Bus Frequency Divider ....................160 11.4.4 Low Power Bit Usage .....................160 11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ..........160 11.4.6 Internal Reference Clock ....................160 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 10 13.3.3 RTC Modulo Register (RTCMOD) ................177 13.4 Functional Description ........................177 13.4.1 RTC Operation Example ....................178 13.5 Initialization/Application Information ..................179 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...........................181 14.1.1 SCI Clock Gating ......................181 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 11 15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........215 15.4 Functional Description ........................217 15.4.1 Counter ..........................217 15.4.2 Channel Mode Selection ....................218 15.5 Reset Overview ..........................221 15.5.1 General ..........................221 15.5.2 Description of Reset Operation ..................222 15.6 Interrupts ............................222 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 12 16.2.2 Communication Details ....................227 16.2.3 BDC Commands ......................230 16.2.4 BDC Hardware Breakpoint .....................233 16.3 Register Definition ........................233 16.3.1 BDC Registers and Control Bits ..................234 16.3.2 System Background Debug Force Reset Register (SBDFR) ..........236 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 13: Chapter 1 Device Overview

    RAM size (bytes) Pin quantity ACMP ADC channels ADC Resolution MTIM Port I/O TPM channels XOSCVLP Package 20-pin TSSOP, 16-pin TSSOP Port I/O count includes the output-only PTA4 and the input-only PTA5 pins. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 14: Mcu Block Diagram

    1 MHz to 16 MHz (XOSC) VOLTAGE REGULATOR pins not available on 16-pin package and V are double bonded to V and V REFH REFL Figure 1-1. MC9S08QL8 Series Block Diagram MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 15: System Clock Distribution

    MC9S08QL8 Series Data Sheet for details. ADC has minimum and maximum frequency requirements. See Chapter 10, Analog-to-Digital Converter (S08ADC12V1) and MC9S08QL8 Data Sheet for details. Figure 1-2. System Clock Distribution Diagram MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 16 TCLK — TCLK is the optional external clock source for the TPM and MTIM modules. The TCLK must be limited to 1/4th the frequency of the bus clock for synchronization. See Chapter 15, Timer/Pulse-Width Modulator (S08TPMV3) Chapter 12, Modulo Timer (S08MTIMV1) more details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 17: Chapter 2 Pins And Connections

    PTB1/KBIP5/TxD/ADP5 PTB5/TPMCH0 PTB2/KBIP6/ADP6 PTB3/KBIP7/ADP7 PTB4 PTC3 PTC0 PTC2 PTC1 Pins shown in bold type are lost in the next lower pin count package. Figure 2-1. MC9S08QL8 Series in 20-Pin TSSOP Package MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 18 Chapter 2 Pins and Connections PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA5/IRQ/TCLK/RESET PTA1/KBIP1/ADP1/ACMP– PTA4/ACMPO/BKGD/MS PTA2/KBIP2/ADP2 PTA3/KBIP3/ADP3 PTB0/KBIP4/RxD/ADP4 PTB7/EXTAL PTB6/XTAL PTB1/KBIP5/TxD/ADP5 PTB5/TPMCH0 PTB2/KBIP6/ADP6 PTB4 PTB3/KBIP7/ADP7 Figure 2-2. MC9S08QL8 Series in 16-Pin TSSOP Packages MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 19: Recommended System Connections

    When PTA4 is configured as BKGD, pin becomes bi-directional When using the XOSCVLP module in low range and low power mode, the external components RF, RS, C1 and C2 are not required. Figure 2-3. Basic System Connections MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 20: Pin Detail

    10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). When using the oscillator in low range and low gain mode, the external components R and C not required. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 21: Reset Pin

    6-pin background debug header, it can hold BKGD/MS low during a POR or after issuing a background debug force reset. This will force the MCU into active background mode. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 22: General-Purpose I/O (Gpio) And Peripheral Ports

    When using the 16-pin device, the user must either enable on-chip pullup devices or change the direction of non-bonded PTC3–PTC0 pins to outputs so the pins do not float. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 23 ACMP+ TPMCH0 pin can be repositioned at PTB5 using TPMCH0PS in SOPT2, default reset location is PTA0. If ADC and ACMP are enabled, both modules will have access to the pin. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 24 Chapter 2 Pins and Connections MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 25: Chapter 3 Modes Of Operation

    Before entering this mode, the following conditions must be met: • FBELP is the selected clock mode for the ICS. • The HGO bit in the ICSC2 register is clear. • The bus frequency is less than 125 kHz. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 26: Active Background Mode

    After entering active background mode, the CPU is held in a suspended state while it waits for serial background commands instead of executing instructions from the user application program. Background commands are of two types: MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 27: Wait Mode

    MCU is operated in run mode for the first time. When the MC9S08QL8 series are shipped from the NXP Semiconductors factory, the flash program memory is erased by default unless specifically noted. As a result, no program can be executed in run mode until the flash memory is initially programmed.

  • Page 28: Stop Modes

    ENBDM is located in the BDCSCR which is accessible only through BDC commands, see Chapter 16, Development Support. When in stop3 mode with BDM enabled, The S will be near R levels because internal clocks are enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 29: Stop2 Mode

    The stop2 recovery time is defined as the interval from the exit trigger to the first opcode fetch. There are three main components to this wakeup time: the voltage regulator recovery time, the clock source start up time, and the reset processing time. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 30: Stop3 Mode

    Typical start up times for the crystal oscillator are also given in the data sheet. Assuming the FLL is the selected clock source upon entering stop3 and the FLL is configured for a 20 MHz ICSOUT frequency, then Equation 3-6 simplifies to MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 31: Active Bdm Enabled In Stop Mode

    Mode Selection Several control signals are used to determine the current operating mode of the device. Table 3-2 shows the conditions for each of the device’s operating modes. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 32 Table 3-2. Power Mode Selections BDCSCR SPMSC1 SPMSC2 Affects on Sub-System Mode of Operation CPU & Periph CLKs Voltage ENBDM LVDE LVDSE PPDC BDM Clock Regulator RUN mode on. ICS in any mode. LPRUN mode low freq required. ICS in standby FBELP mode only.
  • Page 33 LPWAIT WAIT instruction LPWAIT LPRUN Interrupt when LPWUI=0 LPRUN STOP3 STOP instruction STOP3 LPRUN Interrupt when LPWUI=0 LPWAIT Interrupt when LPWUI=1 LPWAIT Not supported WAIT WAIT instruction WAIT Interrupt or reset MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 34: On-Chip Peripheral Modules In Stop And Low Power Modes

    Requires the asynchronous ADC clock. For stop3, LVD must be enabled to run in stop if converting the bandgap channel. The bandgap channel cannot be converted in LPRun or LPWait. LVD must be enabled to run in stop if using the bandgap as a reference. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 35 If LVDSE is set when entering LPRun or LPWait, the MCU will actually enter run or wait mode, respectively. Requires the LVD to be enabled, else in standby. See Section 3.6.4, LVD Enabled in Stop Mode. ERCLKEN and EREFSTEN set in ICSC2, else in standby. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 36 Chapter 3 Modes of Operation MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 37: Chapter 4 Memory

    Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the NXP Semiconductors provided equate file for the MC9S08QL8 series. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 38 0xFFF0:0xFFF1 TPM Overflow Vtpmovf 0xFFF2:0xFFF3 Reserved — 0xFFF4:0xFFF5 Reserved — 0xFFF6:0xFFF7 TPM Channel 0 Vtpmch0 0xFFF8:0xFFF9 Low Voltage Detect or Low Voltage Warning Vlvd 0xFFFA:0xFFFB Virq 0xFFFC:0xFFFD Vswi 0xFFFE:0xFFFF Reset Vreset MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 39: Register Addresses And Bit Assignments

    0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. When writing to these bits, write a 0 unless otherwise specified. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 40 R3/T3 R2/T2 R1/T1 R0/T0 0x0028 — — — — — — — — – Reserved — — — — — — — — 0x0037 0x0038 ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 41 LVWF LVWACK — — LVWIE 0x180C Reserved — — — — — — — — 0x180D Reserved — — — — — — — — 0x180E SCGC1 MTIM 0x180F SCGC2 ACMP MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 42 The internal reference trim values stored in flash, TRIM and FTRIM, can be programmed by third party programmers and must be copied into the corresponding ICS registers by user code to override the factory trim. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 43: Ram

    RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the NXP Semiconductors-provided equate file). LDHX #RamLast+1 ;point one past RAM...

  • Page 44: Flash

    FCLK and as an absolute time for the case where t FCLK shown include overhead for the command state machine and enabling and disabling of program and erase voltages. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 45: Program And Erase Command Execution

    The FCDIV register must be initialized before using any flash command. This must be done only once following a reset. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 46: Burst Program Execution

    • The next burst program command has been queued before the current program operation has completed. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 47 Reads of the flash during program or erase are ignored and invalid data is returned. FPVIOL OR ERROR EXIT FACCERR? NEW BURST COMMAND? FCCF? DONE Figure 4-3. Flash Burst Program Flowchart MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 48: Access Errors

    For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 49: Vector Redirection

    NVOPT location which can be done at the same time the flash memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 50: Flash Registers And Control Bits

    NVPROT) in the nonvolatile register space in flash memory are copied into corresponding high-page control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in flash memory. Refer MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 51: Flash Clock Divider Register (Fcdiv)

    This section refers to registers and control bits only by their names. An NXP Semiconductors-provided equate or header file is normally used to translate these names into the appropriate absolute addresses.

  • Page 52: Flash Options Register (Fopt And Nvopt)

    SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. For more detailed information about security, refer to Section 4.6, Security.” MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 53: Flash Configuration Register (Fcnfg)

    Reset This register is loaded from nonvolatile location NVPROT during reset. Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. Flash Protection Register (FPROT) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 54: Flash Status Register (Fstat)

    (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 55: Flash Command Register (Fcmd)

    All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 56 Chapter 4 Memory MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 57: Chapter 5 Resets, Interrupts, And General System Control

    Low-voltage detect (LVD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 58: Computer Operating Properly (Cop) Watchdog

    When the bus clock source is selected, the COP counter does not increment while the system is in stop mode. The COP counter resumes as soon as the MCU exits stop mode. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 59: Interrupts

    RTI that is used to return from the ISR. If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 60: Interrupt Stack Frame

    (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD) and whether an event causes an interrupt or only sets the IRQF flag which can be polled by software (IRQIE). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 61: Interrupt Vectors, Sources, And Local Masks

    CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 62 SWI Instruction — Software interrupt Highest 0xFFFE/0xFFFF Vreset System COPE Watchdog timer control LVDRE Low-voltage detect RESET pin RSTPE External pin Illegal opcode — Illegal opcode Illegal address — Illegal address MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 63: Low-Voltage Detect (Lvd) System

    The actual clock will be enabled or disabled immediately following the write to the clock gating control registers (SCGC1 and SCGC2). Any MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 64: Reset, Interrupt, And System Control Registers And Control Bits

    This direct-page register includes status and control bits which are used to configure the IRQ function, report status, and acknowledge IRQ events. IRQF IRQPDD IRQEDG IRQPE IRQIE IRQMOD IRQACK Reset = Unimplemented or Reserved Figure 5-2. Interrupt Request Status and Control Register (IRQSC) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 65 Section 5.5.2.2, Edge and Level Sensitivity for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 66: System Reset Status Register (Srs)

    Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 67: System Background Debug Force Reset Register (Sbdfr)

    PTA4/ACMPO/BKGD/MS must be high immediately after issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing WRITE_BYTE command. See the data sheet for more information. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 68: System Options Register 1 (Sopt1)

    PTA5 port as input so that RSTPE is enabled only after the pin is confirmed as "1". By doing so, RESET pin can avoid being low and cause another reset. Mind that COP must be refreshed during pin monitor to prevent unwanted COP reset. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 69: System Options Register 2 (Sopt2)

    Chapter 9, Analog Comparator (S08ACMPVLPV1) Chapter 15, Timer/Pulse-Width Modulator (S08TPMV3) for more details on this feature. 0 ACMP output not connected to TPM input channel 0. 1 ACMP output connected to TPM input channel 0. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 70: System Device Identification Register (Sdidh, Sdidl)

    Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08QL8 is hard coded to the value 0x023. See also ID bits in Table 5-8. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 71: System Power Management Status And Control 1 Register (Spmsc1)

    Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC module on one of its internal channels or as a voltage reference for ACMP module. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 72: System Power Management Status And Control 2 Register (Spmsc2)

    LPR=1. If PPDC and LPR are set in a single write instruction, only PPDC will actually be set. PPDC 0 Stop3 low power mode enabled. 1 Stop2 partial power down mode enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 73: System Power Management Status And Control 3 Register (Spmsc3)

    Table 5-13. LVD and LVW Trip Point Typical Values LVW Trip Point LVD Trip Point = 2.14 V = 1.84 V See MC9S08QL8 Series Data Sheet for minimum and maximum values. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 74: System Clock Gating Control 1 Register (Scgc1)

    SCI Clock Gate Control — This bit controls the clock gate to the SCI module. 0 Bus clock to the SCI module is disabled. 1 Bus clock to the SCI module is enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 75: System Clock Gating Control 2 Register (Scgc2)

    RTC Clock Gate Control — This bit controls the bus clock gate to the RTC module. Only the bus clock is gated, the ICSERCLK and LPOCLK are still available to the RTC. 0 Bus clock to the RTC module is disabled. 1 Bus clock to the RTC module is enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 76 Chapter 5 Resets, Interrupts, and General System Control MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 77: Chapter 6 Parallel Input/Output Control

    In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 78: Pullup, Slew Rate, And Drive Strength

    An output pin can be configured for high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 79: Pin Behavior In Stop Modes

    This section refers to registers and control bits only by their names. An NXP-provided equate or header file is normally to translate these names into the appropriate absolute addresses. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 80: Port A Registers

    PTADD[3:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 81 PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 82: Port B Registers

    0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. 6.4.2 Port B Registers Port B is controlled by the registers listed below. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 83 PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 84 PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 85: Port C Registers

    Port C is controlled by the registers listed below. 6.4.3.1 Port C Data Register (PTCD) — — — — PTCD3 PTCD2 PTCD1 PTCD0 Reset: Figure 6-12. Port C Data Register (PTCD) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 86 PTCDD[3:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 87 PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 88 PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 89: Chapter 7 Keyboard Interrupt (S08Kbiv2)

    To conserve power, this bit can be cleared to disable the clock to this module when not in use. See Section 5.7, Peripheral Clock Gating for details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 90: Features

    KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 7.1.4 Block Diagram The block diagram for the keyboard interrupt module is shown Figure 7-1. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 91: External Signal Description

    The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. Table 7-1. KBI Pin Mapping Port pin PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0 KBI pin KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 92: Register Definition

    KBI Detection Mode — KBIMOD (along with the KBIES bits) controls the detection mode of the KBI interrupt KBIMOD pins. 0 KBI pins detect edges only. 1 KBI pins detect both edges and levels. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 93: Kbi Interrupt Pin Select Register (Kbipe)

    KBIMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitivity can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 94: Edge Only Sensitivity

    4. Enable the interrupt pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 95: Chapter 8 Central Processor Unit (S08Cpuv5)

    (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 96: Programmer's Model And Cpu Registers

    A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 97: Stack Pointer (Sp)

    For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, NXP document order number HCS08RMv1. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 98 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 99: Addressing Modes

    16-bit address where the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit address for the operand. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 100: Extended Addressing Mode (Ext)

    This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 101: Special Operations

    After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 102: Wait Mode Operation

    MCU even if it is in stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to Chapter 3, Modes of Operation for more details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 103: Bgnd Instruction

    Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 104: Hcs08 Instruction Set Summary

    Half carry, bit 4 Interrupt mask, bit 3 Negative indicator, bit 2 Zero indicator, bit 1 Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – Bit not affected MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 105 The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. Address modes Inherent (no operands) 8-bit or 16-bit immediate MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 106  – –    ASR oprx8,X ASR ,X ASR oprx8,SP 9E67 BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 107 – – – – – – BPL rel Branch if Plus Branch if (N) = 0 2A rr – – – – – – BRA rel Branch Always No Test 20 rr MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 108 (H:X) – (M:M + 0x0001) CPHX #opr16i Compare Index Register – – (CCR Updated But Operands Not     CPHX opr8a (H:X) with Memory Changed) CPHX oprx8,SP 9EF3 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 109 Load Index Register (H:X) H:X M:M+ 0x0001 0 – – – LDHX ,X 9EAE   from Memory LDHX oprx16,X 9EBE ee ff LDHX oprx8,X 9ECE LDHX oprx8,SP 9EFE MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 110 – – – – – – PULX Low) from Stack ROL opr8a ROLA ROLX – – Rotate Left through Carry     ROL oprx8,X ROL ,X ROL oprx8,SP 9E69 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 111 Push (A); SP  (SP) – 0x0001 – – 1 – – – Software Interrupt Push (CCR); SP  (SP) – 0x0001 I  1; PCH  Interrupt Vector High Byte PCL  Interrupt Vector Low Byte MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 112 Transfer Index Reg. to SP Enable Interrupts; Wait I bit  0; Halt CPU – – 0 – – – WAIT for Interrupt Bus clock frequency is one-half of the CPU clock frequency. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 113 DIR to DIR IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 114 Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in 9E60 HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 115: Chapter 9 Analog Comparator (S08Acmpvlpv1)

    See Section 5.7, Peripheral Clock Gating for details. 9.1.4 Stop1 Not Available Stop1 is not available on this MCU. Therefore, ignore references the stop1 within this chapter. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 116: Features

    When the microcontroller is in active background mode, the ACMP continues to operate normally. When ACMPO is shared with the BKGD pin and the BKGD pin is enabled, the ACMPO function is not available. 9.1.7 Block Diagram The block diagram for the ACMP module follows. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 117: External Signal Description

    Register Definition 9.3.1 Status and Control Register (ACMPxSC) ACME ACBGS ACIE ACOPE ACMOD1 ACMOD0 Reset: = Unimplemented Figure 9-2. ACMP Status and Control Register (ACMPxSC) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 118: Functional Description

    The ACMP module is capable of generating an interrupt on a compare event. The interrupt request is asserted when both the ACIE bit and the ACF bit are set. The interrupt is deasserted by clearing either the MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 119 Analog Comparator (S08ACMPVLPV1) ACIE bit or the ACF bit. The ACIE bit is cleared by writing a logic zero and the ACF bit is cleared by writing a logic one. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 120 Analog Comparator (S08ACMPVLPV1) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 121: Chapter 10 Analog-To-Digital Converter (S08Adc12V1)

    Table 10-1. ADC Channel Assignment ADCH Channel Input Pin Control ADCH Channel Input Pin Control 00000 PTA0/ADP0 ADPC0 10000 AD16 REFL 00001 PTA1/ADP1 ADPC1 10001 AD17 REFL 00010 PTA2/ADP2 ADPC2 10010 AD18 REFL MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 122 The RTC can be clocked by either ICSIRCLK, OSCOUT or LPO. The period of the RTC is determined by the input clock frequency and the RTC configuration bits. When the ADC hardware trigger is enabled, a conversion is initiated upon a RTC overflow. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 123 V the cold slope value is applied in Equation 10-1. If V TEMP25 TEMP TEMP25 TEMP less than V the hot slope value is applied in Equation 10-1. TEMP25 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 124: Features

    • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.4 ADC Module Block Diagram Figure 10-1 provides a block diagram of the ADC module MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 125: External Signal Description

    The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground connections. Table 10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs High reference voltage REFH Low reference voltage REFL Analog power supply Analog ground MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 126: Analog Power

    This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 127 Table 10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 REFH 11110 REFL 11111 Module disabled MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 128: Status And Control Register 2 (Adcsc2)

    0 Compare triggers when input is less than compare value 1 Compare triggers when input is greater than or equal to compare value MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 129: Data Result High Register (Adcrh)

    In 8-bit mode, there is no interlocking with ADCRH. If the MODE bits are changed, any data in ADCRL becomes invalid. ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Reset: Figure 10-5. Data Result Low Register (ADCRL) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 130: Compare Value High Register (Adccvh)

    Configuration Register (ADCCFG) ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long sample time. ADLPC ADIV ADLSMP MODE ADICLK Reset: Figure 10-8. Configuration Register (ADCCFG) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 131 Divide Ratio Clock Rate Input clock Input clock 2 Input clock 4 Input clock 8 Table 10-8. Conversion Modes MODE Mode Description 8-bit conversion (N=8) 12-bit conversion (N=12) 10-bit conversion (N=10) Reserved MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 132: Pin Control 1 Register (Apctl1)

    1 AD3 pin I/O control disabled ADC Pin Control 2. ADPC2 controls the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 133: Pin Control 2 Register (Apctl2)

    1 AD11 pin I/O control disabled ADC Pin Control 10. ADPC10 controls the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 134: 10Pin Control 3 Register (Apctl3)

    1 AD19 pin I/O control disabled ADC Pin Control 18. ADPC18 controls the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 135: Functional Description

    Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC do not perform according to specifications. If the available clocks MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 136: Input Select And Pin Control

    In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 137 After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5 ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 138 Number of bus cycles = 3.5 s x 8 MHz = 28 cycles NOTE The ADCK frequency must be between f minimum and f ADCK ADCK maximum to meet ADC specifications. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 139: Automatic Compare Function

    Then the conversion result of 0x080 is added to 2’s complement of 0x200: %000 1000 0000 %110 0000 0000 --------------- <= Subtraction result is –0x180 in signed 11-bit data %110 1000 0000 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 140: Mcu Wait Mode Operation

    ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 141: Mcu Stop2 Mode Operation

    1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 142 Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 143: Application Information

    MCU digital supply pins. In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 144 , the converter circuit converts it to 0x000. Input voltages between V and V REFL REFH REFL straight-line linear conversions. There is a brief current associated with V when the sampling REFL MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 145: Sources Of Error

    — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 146 (1 ) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 147 Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 148 Analog-to-Digital Converter (S08ADC12V1) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 149: Chapter 11 Internal Clock Source (S08Icsv3)

    11.1.1 DCO Select bits The ICS on the MC9S08QL8 series is configured to support only the low range DCO, therefore the DRS and DRST bits in ICSSC have no effect. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 150: Features

    Three selectable digitally-controlled oscillators (DCO) optimized for different frequency ranges. • Option to maximize output frequency for a 32768 Hz external reference clock source. 11.1.3 Block Diagram Figure 11-1 is the ICS block diagram. MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 151: Modes Of Operation

    In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied from the FLL. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 152: External Signal Description

    11.3 Register Definition Figure 11-1 is a summary of ICS registers. Table 11-1. ICS Register Summary Name ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN ICSC2 BDIV RANGE EREFS ERCLKEN EREFSTEN ICSTRM TRIM MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 153: Ics Control Register 1 (Icsc1)

    1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop. 0 Internal reference clock is disabled in stop. Table 11-3. Reference Divide Factor RDIV RANGE=0 RANGE=1 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 154: Ics Control Register 2 (Icsc2)

    (OSCOUT) remains enabled when the ICS enters stop mode. 1 External reference clock source stays enabled in stop if ERCLKEN is set before entering stop. 0 External reference clock source is disabled in stop. MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 155: Ics Trim Register (Icstrm)

    32.768 kHz reference. See Table 11-7. 0 DCO has default range of 25%. 1 DCO is fined tuned for maximum frequency with 32.768 kHz reference. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 156 31.25 - 39.0625 kHz 1536 48 - 60 MHz 32.768 kHz 1824 59.77 MHz Reserved The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 157: Functional Description

    The FLL loop locks the frequency to the FLL factor times the internal reference frequency. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 158 RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • BDM mode is active or LP bit is written to 0. MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 159: Mode Switching

    DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the DRST bits. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 160: Bus Frequency Divider

    All MCU devices are factory programmed with a trim value in a reserved memory location. This value is uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer precision, trim the internal oscillator in the application and set the FTRIM bit accordingly. MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 161: External Reference Clock

    The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low power (FBILP) and FLL bypassed external low power (FBELP) modes. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 162 Internal Clock Source (S08ICSV3) MC9S08QL8 MCU Series Reference Manual, Rev. 0 NXP Semiconductors...

  • Page 163: Chapter 12 Modulo Timer (S08Mtimv1)

    To conserve power, the MTIM bit can be cleared to disable the clock to this module when not in use. See Section 5.7, Peripheral Clock Gating for details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 164: Features

    The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written to a 1 or MTIMMOD written). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 165: Block Diagram

    The TCLK pin can be muxed with a general-purpose port pin. See Chapter 2, Pins and Connections for the pin location and priority of this function. 12.3 Register Definition Figure 12-2 is a summary of MTIM registers. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 166 MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 167: Mtim Status And Control Register (Mtimsc)

    TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. Unused register bits, always read 0. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 168: Mtim Clock Configuration Register (Mtimclk)

    0110 Encoding 6. MTIM clock source  64 0111 Encoding 7. MTIM clock source  128 1000 Encoding 8. MTIM clock source  256 All other encodings default to MTIM clock source  256. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 169: Mtim Counter Register (Mtimcnt)

    MTIM Modulo — These eight read/write bits contain the modulo value used to reset the count and set TOF. A value of 0x00 puts the MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to 0x00 and clears TOF. Reset sets the modulo to 0x00. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 170: Functional Description

    MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE should never be written to a 1 while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 171: Mtim Operation Example

    The timer overflow flag, TOF, sets when the counter value changes from 0xAA to 0x00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 172 Modulo Timer (S08MTIMV1) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 173: Chapter 13 Real-Time Counter (S08Rtcv1)

    RTC for proper operation. Interrupts from the RTC will not occur if the bus clock is gated off. See Section 5.7, Peripheral Clock Gating for details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 174: Features

    The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 175: Block Diagram

    RTC registers.This section refers to registers and control bits only by their names and relative address offsets. Table 13-1 is a summary of RTC registers. Table 13-1. RTC Register Summary Name RTCSC RTIF RTCLKS RTIE RTCPS RTCCNT RTCCNT RTCMOD RTCMOD MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 176: Rtc Status And Control Register (Rtcsc)

    See Table 13-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS. Table 13-3. RTC Prescaler Divide-by values RTCPS RTCLKS[0] 5x10 2x10 5x10 2x10 5x10 2x10 MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 177: Rtc Counter Register (Rtccnt)

    (ERCLK), and the internal clock (IRCLK). The RTC clock select bits (RTCLKS) select the desired clock source. If a different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 178: Rtc Operation Example

    (RTIE) in RTCSC. RTIF is cleared by writing a 1 to RTIF. 13.4.1 RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 179: Initialization/Application Information

    /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 180 /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 181: Chapter 14 Serial Communications Interface (S08Sciv4)

    To conserve power, this bit can be cleared to disable the clock to this module when not in use. See Section 5.7, Peripheral Clock Gating for details. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 182 Rx/Tx pin Tx data path direction in polarity single-wire mode R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SCID Read: Rx data; write: Tx data Figure 14-1. SCI Module Quick Start MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 183: Features

    SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode 14.1.4 Block Diagram Figure 14-2 shows the transmitter portion of the SCI. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 184 SCI CONTROLS TxD TO TxD TRANSMIT CONTROL PIN LOGIC TxD DIRECTION TXDIR BRK13 TDRE Tx INTERRUPT REQUEST TCIE Figure 14-2. SCI Transmitter Block Diagram Figure 14-3 shows the receiver portion of the SCI. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 185 WAKEUP RWUID LOGIC ACTIVE EDGE DETECT RDRF IDLE ILIE Rx INTERRUPT REQUEST LBKDIF LBKDIE RXEDGIF RXEDGIE ORIE FEIE ERROR INTERRUPT REQUEST NEIE PARITY CHECKING PEIE Figure 14-3. SCI Receiver Block Diagram MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 186: Register Definition

    When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 14-2. SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset Figure 14-5. SCI Baud Rate Register (SCIBDL) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 187: Sci Control Register 1 (Scic1)

    10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 14.3.3.2.1, Idle-Line Wakeup for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 188: Sci Control Register 2 (Scic2)

    When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 189: Sci Status Register 1 (Scis1)

    This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 14-8. SCI Status Register 1 (SCIS1) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 190 NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID). 0 No noise detected. 1 Noise detected in the received character in SCID. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 191: Sci Status Register 2 (Scis2)

    0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 192: Sci Control Register 3 (Scic3)

    (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 193: Sci Data Register (Scid)

    The following describes each of the blocks of the SCI. 14.3.1 Baud Rate Generation As shown in Figure 14-12, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 194: Transmitter Functional Description

    If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 195: Receiver Functional Description

    After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 196 (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 197: Interrupts And Status Flags

    If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 198: Additional Sci Functions

    Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 199 In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 200 Serial Communications Interface (S08SCIV4) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 201: Chapter 15 Timer/Pulse-Width Modulator (S08Tpmv3)

    The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any considerations that should be taken when porting code. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 202 TPM counter (end of the prescaler counting) after the second byte is written. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 203 Mode. [SE110-TPM case 1] For more information, refer to Section 15.4.2.4, Center-Aligned PWM Mode. [SE110-TPM case 2] For more information, refer to Section 15.4.2.4, Center-Aligned PWM Mode. [SE110-TPM case 3 and 5] MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 204: Migrating From Tpmv1

    0xFFFE to 0xFFFF). Reseting the coherency mechanism for the Write to TPMxSC. Channel Value Register (TPMxCnV) register... Configuring the TPM modules... Write first to TPMxSC and then to TPMxCnV register. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 205: Features

    MCU pin. The output compare action is selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). • Edge-aligned PWM mode MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 206: Block Diagram

    Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 207 CH1IE MS1B MS1A up to 8 channels ELS7B ELS7A Port channel 7 TPMxCH7 logic 16-bit comparator TPMxC7VH:TPMxC7VL CH7F Interrupt 16-bit latch logic CH7IE MS7B MS7A Figure 15-1. TPM Block Diagram MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 208: Signal Description

    ELSnB:ELSnA  0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bits determine what polarity edge or edges trigger input capture events. The channel input signal is synchronized on the bus clock. This implies the minimum pulse width—that can MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 209 PWM output signal. If ELSnB is set and ELSnA is cleared, the corresponding TPMxCHn pin is cleared when the TPM counter is counting up, and the channel value register matches the TPM counter; and it is MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 210 CHnF bit TOF bit Figure 15-4. High-true pulse of a center-aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF bit TOF bit Figure 15-5. Low-true pulse of a center-aligned PWM MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 211: Register Definition

    TPM counter. The new prescale factor affects the selected clock on the next bus clock cycle after the new value is updated into the register bits. Table 15-6. TPM Clock Selection CLKSB:CLKSA TPM Clock to Prescaler Input No clock selected (TPM counter disable) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 212: Tpm-Counter Registers (Tpmxcnth:tpmxcntl)

    TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. TPMxCNT[15:8] Any write to TPMxCNTH clears the 16-bit counter Reset Figure 15-7. TPM Counter Register High (TPMxCNTH) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 213: Tpm Counter Modulo Registers (Tpmxmodh:tpmxmodl)

    BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. TPMxMOD[15:8] Reset Figure 15-9. TPM Counter Modulo Register High (TPMxMODH) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 214: Tpm Channel N Status And Control Register (Tpmxcnsc)

    Mode select B for TPM channel n. When CPWMS is cleared, setting the MSnB bit configures TPM channel n for MSnB edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in Table 15-9. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 215: Tpm Channel Value Registers (Tpmxcnvh:tpmxcnvl)

    These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. TPMxCnV[15:8] Reset Figure 15-12. TPM Channel Value Register High (TPMxCnVH) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 216 BDM is active do not interfere with partial completion of a coherency sequence. After the coherency mechanism is fully exercised, the channel registers are updated using the buffered values (while BDM was not active). MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 217: Functional Description

    However, this channel can be used in output compare mode with ELSnB:ELSnA = 0:0 for software timing functions. In this case, the channel output is disabled, but the channel match events continue to set the appropriate flag. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 218: Channel Mode Selection

    (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge is chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 219 PWM signal low. If ELSnA is set, the counter overflow forces the PWM signal low, and the channel match forces the PWM signal high. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 220 When CPWMS is cleared, this case corresponds to the counter running free from 0x0000 through 0xFFFF. When CPWMS is set, the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 221: Reset Overview

    When TPMxCNTH:TPMxCNTL equals TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). 15.5 Reset Overview 15.5.1 General The TPM is reset whenever any MCU reset occurs. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 222: Description Of Reset Operation

    If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 223 PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described in Section 15.6.2, Description of Interrupt Operation. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 224 Timer/Pulse-Width Modulator (S08TPMV3) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 225: Chapter 16 Development Support

    MCU will always reset into normal operating mode. 16.1.2 Module Configuration The alternate BDC clock source is the ICSLCLK. This clock source is selected by clearing the CLKSW bit in the BDCSCR register. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 226: Features

    However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 227: Bkgd Pin Description

    MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 228 MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 229 HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 230: Bdc Commands

    HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 16-1 to describe the coding structure of the BDC commands. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 231 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 232 Increment H:X by one, then write memory byte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. The SYNC command is a special operation that does not have a command code. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 233: Bdc Hardware Breakpoint

    The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. 16.3 Register Definition This section contains the descriptions of the BDC registers and control bits. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 234: Bdc Registers And Control Bits

    WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 235 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...

  • Page 236: System Background Debug Force Reset Register (Sbdfr)

    This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 237 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 238 Development Support MC9S08QL8 MCU Series Reference Manual, Rev. 1 NXP Semiconductors...
  • Page 240 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.

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